@S1-A.ARPA,@MIT-MC.ARPA:GUBBINS@RADC-TOPS20.ARPA (06/20/85)
From: Gern <GUBBINS@RADC-TOPS20.ARPA> It is my understanding that the Space Shuttle computers are 32-bit machines (IBM does not seem to make 36-bit machines) and are a scaled down version of the IBM 360 in a 60 pound package (gross!). That is, 4 of the computers are. The 5th was designed and built by Rockwell (Rockwell doesn't trust IBM computers either). I do not know how different the Rockwell machine is to the IBMs, but it is the only computer that has never failed (it did cause the sync problems on the very first attempted launch, but only because the 4 IBMs ganged up on it...). Cheers, Gern -------
@S1-A.ARPA,@MIT-MC.ARPA:JOSH%YKTVMH.BITNET@WISCVM.ARPA (06/21/85)
From: Josh Knight <JOSH%YKTVMH.BITNET@WISCVM.ARPA>
The September 1984 Issue of Communications of the ACM had a case study
of the Space Shuttle primary computer system and a special section on
on computing in space. The following excerpt from the (copyright ACM)
case study article "The Space Shuttle Primary Computer System" by Alfred
Spector and David Gifford, is a response by Tony Macina of IBM to the
question by Al Spector "Can you give us some more detailed information
about the Shuttle computers?":
"A single computer (GPC) is made up of two packages, a CPU unit
and an I/O device unit (IOP), with a total of 106K 32 bit words of
memory. The CPU, a System/4 Pi, Model AP-101 manufactured by IBM
is an off-the-shelf processor and has probably been around for 10
or 12 years. Our original contract specified that we use off-the-
shelf hardware as much as possible. The 4 Pi design has been used
in a number of other aerospace vehicles. For example, certain B-52
aircraft an the B-1 Bomber use 4 Pi technology.
"The IOP was specially built and designed for the Shuttle, using
4 Pi technology. It contains 24 "time-sliced" processors that handle
the data buses on the Shuttle. The IOP obtains its instructions from
the main memory and is actually in contention with the CPU for memory
access."
Further responses indicate that the main memory is ferrite core (non-
volatility is cited as an advantage of this old implementation), that
the CPU processes 450,000 instructions/second and that the CPU/IOP
combination weighs about 120 pounds. To control flight surfaces each
of the 4 (hopefully) identical computers send independent commands on
independent buses to independent actuators and what happens to the
control surfaces is controlled by a HYDRAULIC "voting" mechanism.
The articles in the special section on computing in space are:
"Development and Application of NASA's First Standard Spacecraft
Computer" by C.E. Trevathan, T.D. Taylor, R.G. Hartenstein,
A.C. Merwarth and W.N. Stewart
"Design, Devlopment, Integration: Space Shuttle Primary Flight
Software System" by W.A. Madden and K.Y. Rone
"Architecture of the Space Shuttle Primary Avionics Software System"
by G.D. Carlow
Of course, any opinions, expressed or implied are mine and not my employers...
Josh Knight
IBM T.J. Watson Research Center
josh@yktvmh.BITNET, josh.yktvmh.ibm-sj@csnet-relay.ARPA@S1-A.ARPA,@MIT-MC.ARPA:cdl@cmu-cs-k.arpa (06/21/85)
From: Douglass.Locke@CMU-CS-K.ARPA The four (not five) Shuttle computers are indeed IBM AP-101 processors. They are environmentally hardened 32 bit machines which bear NO resemblance to IBM 360's or any other commercial computer, either in architecture or in construction. Although all the processors are identical, one contains a different software package written by Rockwell to avoid the potential of a single software problem stopping all the computers simultaneously. Before one criticizes the packaging, or the memory technology chosen, it would perhaps be appropriate to investigate the difficulties of handling an environment with potential extremes of temperature, vibration, shock, EMI, and radiation, with acceptable reliability, and in a vehicle which is totally dependent on the equipment. When NASA was specifying the equipment, it was in the mid-70's and there was no applicable experience with the actual shuttle environment, so a conservative approach was certainly justified. The IBM AP-101 is one of an extensive line of machines for such environments with a variety of speeds, form factors, memory technologies, etc., each designed to cope with different environmental and application requirements. -- Doug Locke
fisher@dvinci.DEC (06/28/85)
<>
> ...the fifth one is different from the other 4; it is made by Rockwell...
I could be proven wrong, but I am quite sure that all 5 cpus are the same.
The fifth one, however, was PROGRAMMED by Rockwell rather than IBM. The
quintuple hardware redundancy provides backup for hardware failure. The
separate program for #5 provides a backup for the software.
BTW, the 5 computers only run as a quintuple redundant set during critical
phases of the mission (ascent and decent, and perhaps during some of the
prelaunch activities). At other times, they are decoupled and given separate
tasks, with only double or triple redundancy for such things as orbital
calculations, environment management, and running the arm.
Burns
UUCP: ... {decvax|allegra|ucbvax}!decwrl!rhea!dvinci!fisher
ARPA: fisher%dvinci.dec@decwrl.ARPAeder@ssc-vax.UUCP (Dani Eder) (07/06/85)
> <> > > ...the fifth one is different from the other 4; it is made by Rockwell... > > I could be proven wrong, but I am quite sure that all 5 cpus are the same. > The fifth one, however, was PROGRAMMED by Rockwell rather than IBM. The > quintuple hardware redundancy provides backup for hardware failure. The > separate program for #5 provides a backup for the software. > > BTW, the 5 computers only run as a quintuple redundant set during critical > phases of the mission (ascent and decent, and perhaps during some of the > prelaunch activities). At other times, they are decoupled and given separate > tasks, with only double or triple redundancy for such things as orbital > calculations, environment management, and running the arm. The following is extracted from a Rockwell International reference book on the space shuttle: The memory capacity of each CPU is 81,920 words. The memory capacity of each input-output processor (which intermediates between CPU and real world) is 24,576 words. To accomplish all of the mission phases, approx. 400,000 woeds are required. To fit the software, it has been divided into 9 parts. Mass memory is provided by two tape drives totalling 37 Meg. Each I/O Processor contains 24 processors, each controlling one data bus. The computers perform 325000 operations/second, and when operating in a redundant mode compare results 440 times/second. Each CPU is 7 1/2 x 10 x 19 inches and weighs 57 pounds. The I/O processors are the same size and weight. Each of two mass memories is 7 1/2 x 11 x 15 inches and weights 22 lbs. Dani Eder/ Boeing Advanced Space Transportation Organization/ssc-vax!eder >