gilgalad@caen.engin.umich.edu (Ralph Seguin) (11/02/90)
With all this talk of plopping RISC boards into your Amiga, I've had a question that's been nagging me: Is that beautiful piece of code we call Exec going to allow for scheduling, recognition, ..., on multiple processors (of different sorts)? Symmetric MultiProcessing (oooh, nice buzzword 8-)? It would really be nice to have Exec worry about what is to be executed where. Have your Amiga with an ethernet board, and an i860 board (with 8 processors of course 8-), an 88000 board, and a MIPS R3000 board, and you have a serious compute server. Machines will be doing RPCs to your machine left and right. Thus we have the need for ..., yep you guessed it, FDDI. I asked this before, but is anybody working on an FDDI board for the Amiga? Granted an 030 could not produce data fast enough to fill that kind of bandwidth, but we're not going to be sticking with 030 for long...8-) Hey Amiga crew, how about it? FDDI in the 4000, as well as ethernet and Token Ring (Don't care too much for Token myself). OS people, let's have support for a heterogeneous network of processors, and transparent scheduling, etc. Thanks, Ralph Ralph Seguin gilgalad@dip.eecs.umich.edu 536 South Forest Apt. #915 gilgalad@caen.engin.umich.edu Ann Arbor, MI 48104 (313) 662-4805
jdickson@jato.jpl.nasa.gov (Jeff Dickson) (11/03/90)
Newsgroups: comp.sys.amiga.tech,comp.sys.amiga.hardware Subject: Re: RISC Amiga and multiprocessing Summary: Expires: References: <1990Nov2.070729.19128@engin.umich.edu> Sender: Reply-To: jdickson@jato.Jpl.Nasa.Gov (Jeff Dickson) Followup-To: Distribution: na Organization: Jet Propulsion Laboratory, Pasadena, CA Keywords: This is merely speculation. I find it difficult to believe that CBM could one day dump Motorola CPU's and take on say Intel's. What leads me to this speculation are the major differences in Motorola's and Intel's bus philosophy. For one, Motorola goes for memory mapped I/O while Intel goes for non memory mapped I/O. Another, Motorola has a more robust bus handshaking protocol. Motorola CPU's say "here it is" and the type of bus cycle lasts until whoever got it says "OK. I got it". Intel CPU's say "Go for it" and its up to who ever it is for to assert wait cycles if more time is needed. I also believe there are big differences in interupts and interupt levels. Seems that gearing the Amiga for a non Motorola CPU at this time, would involve a major overhaul. Please execuse my ignorance in this matter if I am partially mistaken. The above argument was valid for some older CPUs - believe it still is. Jeff -------------------------------------------------------------------------- Jeff S. Dickson jdickson@zook.jpl.nasa.gov
brian@sky.COM (Brian Pelletier) (11/03/90)
In article <1990Nov2.190352.5801@jato.jpl.nasa.gov> jdickson@jato.Jpl.Nasa.Gov (Jeff Dickson) writes: > > This is merely speculation. I find it difficult to believe that ^^^^^^^^^^^^ Yes. But unfortunately a bit misinformed.... > [Much stuff about 80x86 type processors] The i860 is *not* an 80x86 spinoff, and has none of the traditional Intel CPU 'mis-features' that you speak of. It's a brand new architecture for Intel, and its interrupt and bus cycle handling are similar to other RISC processors on the market. -Brian +=========================================================================+ | Brian Pelletier Disclaimer: These are MY opinions, not SKY's.| | Sky Computer | | UUCP - brian@sky.com (work) pelletier@grove.UUCP (home) | +=========================================================================+
daveh@cbmvax.commodore.com (Dave Haynie) (11/06/90)
In article <1990Nov2.190352.5801@jato.jpl.nasa.gov> jdickson@jato.Jpl.Nasa.Gov (Jeff Dickson) writes: > This is merely speculation. I find it difficult to believe that >CBM could one day dump Motorola CPU's and take on say Intel's. As I said before, I don't really expect anything called an "Amiga" to run with a non-Motorola 680x0 family CPU as it's heart, simply because of software compatibility issues. That doesn't imply that other CPUs couldn't find a useful place in an Amiga; in fact, some alternate CPUs are available today as plug ins. >What leads me to this speculation are the major differences in Motorola's >and Intel's bus philosophy. For one, Motorola goes for memory mapped I/O >while Intel goes for non memory mapped I/O. That's primarily a feature of Intel 80x86 CPUs; I don't think there are any RISC CPUs or other new interesting processors, from Intel or anyone else, that work that way now. It's not a problem anyway, since any hardware in special "I/O memory" can be remapped as memory mapped hardware very simply when you're designing the system. Or, more to the point, just because you have special I/O instructions doesn't mean you have to use them -- an 80386 can do memory mapped I/O if you put it in a memory mapped system. This silly I/O mapping was really only useful back in the days of 8 bit CPUs; the special I/O instructions on 8080 and Z-80 let you have all 64K of address spaced devoted to ROM and RAM, while still letting you at some I/O registers. Most of the 6502 based systems had memory banking of some kind to overlay memory and I/O as needed. >Another, Motorola has a more robust bus handshaking protocol. Motorola CPU's >say "here it is" and the type of bus cycle lasts until whoever got it says >"OK. I got it". Intel CPU's say "Go for it" and its up to who ever it is for >to assert wait cycles if more time is needed. Again, this is the older 80x86 line, and it's quite simple to convert one type of cycle structure into another. I don't think we'll have to worry about glomping 80386s onto Amiga chips, and most likely, any add-on CPU that's not a 680x0 family memory belongs on the Zorro III bus, which is relatively CPU family independent. >I also believe there are big differences in interupts and interupt levels. That's an issue with ISA bus more than 80x86. The ISA bus used edge sensitive active high interrupts, which made it impossible to share interrupts between multiple cards. Silly, since the level sensitive active low interrupts used on the Amiga bus, which permit sharing of interrupt lines, were quite common in the systems that preceeded the first XT and AT bus machines. I gather that EISA and MCA bus both allow interrupt sharing. >Jeff S. Dickson jdickson@zook.jpl.nasa.gov -- Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy Standing on the shoulders of giants leaves me cold -REM
markv@kuhub.cc.ukans.edu (12/19/90)
> This is merely speculation. I find it difficult to believe that > CBM could one day dump Motorola CPU's and take on say Intel's.... > Seems that gearing the Amiga for a non Motorola CPU... As a PC programmer also, all I can say is I don't want an Intel CPU!!!!!!!! Segmented address space (yuck, and I *know* about the 386...), backwords byte ordering (makes network programming a pain), etc. I'll take a Motorola CPU over an Intel any day (esp a 040 :-)). > Jeff S. Dickson jdickson@zook.jpl.nasa.gov > -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Mark Gooderum /\ \ | / H a p p y Academic Computing Services / v\ -- * -- H o l i d a y s ! :-) University of Kansas /v v\ / | \ /// /__v___\ Only /// /| __ _ Bitnet: MARKV@UKANVAX || \\\ /// /__| |\/| | | _ /_\ makes it Internet: markv@kuhub.cc.ukans.edu \/\/ / | | | | |__| / \ possible ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~