chris@tharr.UUCP (Chris Allen) (12/29/90)
I have been hacking at an A500 1.5MB expansion board, trying
to configure it to give a total of 1MB of chip RAM in my A500.
At present it gives 1.5MB of "Fast" RAM located at C00000, using
three banks of 256Kx4 chips.
I thought that to operate with 1MB chip RAM on an 8372 Agnus, the
following was necessary:
1. Change JP2 on the motherboard.
2. Ensure that bank 1 of the RAM appears at 080000 and banks 2 and 3 at
C00000. This is done by demultiplexing A19 and A23 on the processor
address bus, and using the result to feed CAS to one of three banks
of RAM.
This appeared to work at first, but after some experimenting I found
that the Amiga would crash quite consistently when the second half
meg of chip RAM was used.
As far as I can tell, the following sequence of events happens:
1. Agnus is accessing the second half meg of chip RAM independently
of the processor.
2. The processor decides that it wants to access RAM at C00000 which
is also on the RAM board. It places C00000 on the address bus and
waits for a DTACK from GARY.
3. Unfortunately, the address multiplexor on the RAM board gets switched
over when C00000 is put on the bus so Agnus suddenly finds itself
accessing the wrong bank of RAM. Disaster ensues!
The solution to this would *appear* to be the "BLIT" or "DBR" line
running from Agnus to Gary which apparently tells when Agnus is
accessing chip RAM. I have tried using this signal to ensure that
whenever it goes low, the chip RAM on the board is always selected.
However whenever the machine is set up like this, it goes through
its initial memory check then presents me with a yellow screen.
I am mystified. If anybody has more info on the BLIT/DBR line or some
other way of telling when Agnus is accessing chip RAM, I would be
very glad to hear from you!
chris.
--
chris@tharr.uucp ..!ukc!axion!tharr!chris
Disclaimer: The views expressed above are those of my employer..
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