maniac@magic.cs.unlv.edu (Eric J. Schwertfeger) (01/26/91)
As the title line says, I'm looking for some information so I can start on a 14 mhz Accellerator for my A500. Unlike all accellerators available that I know of, this will have zero-wait-state memory, to take advantage of the speed of the processor. First Problem: The only data sheets I could find at our library for megabit dynamic memory are for the Hitachi HM511000. What I need is the pin-outs for 256 by 4 DRAMs. I also need to know if most or all the varous manufacturer`s megabit DRAMs support CAS-Before-RAS refreshing. If the chips don't support that style of refreshing, what is a decent and inexpensive DRAM controller, where can I get it, and where can I get data sheets for it? My goal is to produce plans for a PD accellerator project that 1) Correctly handles the E-Clock 2) Has at least 1 Meg of zero wait memory, possibly autoconfiguring. 3) Can be built for under $150, with memory 4) Preferably doesn't use PALs, so you don't need to any non-off-the-shelf parts. Besides, I don't have access to a PAL programmer, and don't care to build one. I also plan on finding out if the 12.5 Mhz 68010 can be pushed to 14.2 Mhz. At less than 15% over the normal clock speed, this should work :-) -- Eric J. Schwertfeger, maniac@jimi.cs.unlv.edu