frix@hexagon.se (Fredrik Rothamel) (04/04/91)
I've got this small question... Does anyone have som info on 68000 signal timing ? I'm currently interested in how long the processor can wait for a DTACK signal, but info on other signals would also be great. Thanx in advance. -- -- The above expressed opinions are completely my own. -- Fredrik Rothamel Fidonet 2:204/117.3 frix@hexagon.se ...!sunic!kullmar!pkmab!hexagon!frix
knurlin@spf.trw.com (Scott Karlin) (04/06/91)
In article <3319@hexagon.se> frix@hexagon.se (Fredrik Rothamel) writes: >Does anyone have some info on 68000 signal timing ? You need to get a copy of the "M68000 User's Manual" (ISBN 0-13-567074-8) for the 68000 signal timing. >I'm currently interested in how long the processor can wait for a DTACK >signal, but info on other signals would also be great. A 68000 will wait forever for the DTACK signal. (Since this wouldn't be a very social thing to do on the Amiga, a DTACK signal is automatically generated for the Zorro-II boards. One has to do extra work to delay the automatically generated signal.) -- Scott Karlin knurlin@spf.trw.com -- TRW Data Systems Center Phone: (213) 812-7335 -- One Space Park, O2-1761 -- Redondo Beach, CA 90278-1071
jmasters@fxrs.intel.com (Justin Masters) (04/06/91)
In article <3319@hexagon.se> frix@hexagon.se (Fredrik Rothamel) writes: |I've got this small question... | |Does anyone have som info on 68000 signal timing ? I have the book on the spec-book for the 68000 in front of me. Shhhhh... don't tell my boss. Actually, I'm taking a course, so I have to have it. | |I'm currently interested in how long the processor can wait for a DTACK |signal, but info on other signals would also be great. It's DTACK# (active low) Well, let's just say that for an asynchronous operation (which DTACK# is used for) the processor can wait a loooong time, unless something terminates the bus cycle. DTACK# is a "Data Transfer ACKnowledge" signal. If used in a read cycle, DTACK# is asserted, the data is latched on the data bus and the bus cycle ends. If in a write cycle, when DTACK# is asserted, it assumes that the data was accepted by whatever peripheral requested the data, and ends the bus cycle. If DTACK# is not seen in S4 (S0-S7 consitutes a bus cycle), then wait states are generated, and the bus cycle doesn't end, unless ended by some other bus termination method (reset, bus error, address errors, trace, interrupts, illegal instructions, privilege violations, TRAP, TRAPV, CHK and zero divide exceptions). Hope that helps. :-) The data manual is really cheap. I bought mine from a college bookstore for $1.35. | |Thanx in advance. |-- | -- The above expressed opinions are completely my own. -- |Fredrik Rothamel Fidonet 2:204/117.3 |frix@hexagon.se ...!sunic!kullmar!pkmab!hexagon!frix -- "He also emphasized that the glossy advertising circulars, etc., are instant death to all who eat them." - Jessica Mix Barrington --------------------------------------------------------------------------- Justin Masters jmasters@fws136.intel.com
<LEEK@QUCDN.QueensU.CA> (04/07/91)
In article <3319@hexagon.se>, frix@hexagon.se (Fredrik Rothamel) says: > >I'm currently interested in how long the processor can wait for a DTACK >signal, but info on other signals would also be great. A 68000 can wait forever ALONE. The 68000 in an Amiga have to run around from time to time to service interrupts. If it is idle for too long, missing chars from serial ports, messed up timer devices, jerky mouse pointers and/or crashes might crawl on you. :( >Fredrik Rothamel Fidonet >2:204/117.3 >frix@hexagon.se >...!sunic!kullmar!pkmab!hexagon!frix K. C. Lee Elec. Eng. Grad. Student
rda184s@monu6.cc.monash.edu.au (Richard Jones) (04/08/91)
Try the Amiga System Programmers Guide, or one of the many Motorola
guidebooks
Richard Jones,
rda184s@monu6.cc.monash.edu.au
------------------------- OBLIGATORY WITTY QUOTE ---------------------------
The telephone pole was approaching fast. I was attempting to swerve out
of its path when it struck my front end.
-- Seen on an insurance formskipper@motaus.sps.mot.com (Skipper Smith) (04/09/91)
In article <3319@hexagon.se> frix@hexagon.se (Fredrik Rothamel) writes: >I've got this small question... > >Does anyone have som info on 68000 signal timing ? > >I'm currently interested in how long the processor can wait for a DTACK >signal, but info on other signals would also be great. > >Thanx in advance. >-- > -- The above expressed opinions are completely my own. -- >Fredrik Rothamel Fidonet 2:204/117.3 >frix@hexagon.se ...!sunic!kullmar!pkmab!hexagon!frix The answer for your question in theory is "forever" but it turns out that this is not the case on the Amiga since the Zorro II spec indicates that /DTACK will be generated automatically and you have to prevent it. If what you really want is the specs for the 68000 then please contact: Motorola Ltd. European Literature Center 88 Tanners Drive Blakelands Milton Keynes, MK145BP, England or The sales office in (ugh, I missed where you are from. If Sweden is not correct, write back to me and I will give you the right number) Sweden at (08)83 02 00- that is in Solna And ask for the MC68000UM and timing specifications (they are separate now, at least in the English version- although I don't know if we write our manuals in any other language). -- Skipper Smith | skipper@motaus.sps.mot.com Motorola Technical Training | 8945 Guilford Rd Ste 145 All opinions are my own, not my employers | Columbia, MD 21046