rudolpe@jacobs.CS.ORST.EDU (Eric Hans Rudolph) (04/13/91)
Okay, I am here in the lab on the logic analyzer and have found out a couple of things... First, if you use a 500, and want to get a 14mhz signal from XORing CDAC* and 7, don't pull it off of the Expansion IO slot. The signal is WAY funny and when you XOR it with 7, it gives a bad stomach ache. Pull the CDAC off of agnus. It's better shaped and will provide a clean 14Mhz. The rising edge is kinda humpy, but maybe my chip is slow. It's only LS. Furthermore, and I haven't found a solution yet, when you double the clock speed, of course the cycle should be shorter. AS* will go low and the CPU will wait for DTACK* or VPA*. If you sync up the DTACK* with the 7MHZ clock, so that supposedly it will end on a correct cycle, on some memory reads, the REAL DTACK* STILL STAYS ASSERTED. If the cycle was a slow 7mhz one, it would have been deasserted at the end of state 6/7, however, in the faster mode, it overlaps into the next cycle. My first impression is that to fix this, one needs to hold of generating AS* to the device until the old DTACK* deasserts. Can anybody clarify me on this subject??? This is .hardware...! The above circuit design I am talking about is the New 14mhz hack, which doesn't work. I think I am close to providing one that does. Also, just DON'T use LS chips. They are way too slow. rudolpe@jacobs.cs.orst.edu
daveh@cbmvax.commodore.com (Dave Haynie) (04/20/91)
In article <1991Apr13.073956.29605@lynx.CS.ORST.EDU> rudolpe@jacobs.CS.ORST.EDU (Eric Hans Rudolph) writes: >Okay, I am here in the lab on the logic analyzer and have found out a couple >of things... First, if you use a 500, and want to get a 14mhz signal from >XORing CDAC* and 7, don't pull it off of the Expansion IO slot. The signal >is WAY funny and when you XOR it with 7, it gives a bad stomach ache. That's certainly possible, though you may be able to get a better CDAC* at the expansion port by messing around with various termination schemes. And, of course, keeping the path between A500 and expansion board as short as possible. I don't have lots of experience with A500s, and since you almost have to go inside to get 7MHz anyway (unless you build a clever clock doubling circuit based on CDAC*, which can be done), this isn't really vital to the discussion. >It's only LS. I would strongly recommend F or ACT for most 14MHz and above work. Expecially in dealing with clocks. >Furthermore, and I haven't found a solution yet, when you double the >clock speed, of course the cycle should be shorter. AS* will go low >and the CPU will wait for DTACK* or VPA*. If you sync up the DTACK* with >the 7MHZ clock, so that supposedly it will end on a correct cycle, on some >memory reads, the REAL DTACK* STILL STAYS ASSERTED. If the cycle was a >slow 7mhz one, it would have been deasserted at the end of state 6/7, >however, in the faster mode, it overlaps into the next cycle. My first >impression is that to fix this, one needs to hold of generating AS* to >the device until the old DTACK* deasserts. The trick is, you never directly use the real DTACK*. I generally line up things something like this (I had a good day, and got a new coffee cup, so I'll draw a picture here): s0 s1 s2 s3 s4 s5 s6 s7 7M ____----____----____----____----____----____ 7MHz clock 0 1 2 3 w w w w w w w w w w 4 5 6 7 14M --__--__--__--__--__--__--__--__--__--__--__ 14MHz clock AS14M* ---------______________________________----- 14MHz AS* ASEN* ------------____________________------------ AS* Gate to 7MHz bus AS* -------------____________________----------- 7MHz AS* DTKEN* --------------------____________------------ DTACK Gate to 7MHz bus DTACK* xxxxxxxxxxxxxxxxxx----__________xxxxxxxxxxxx 7MHz DTACK* DTK14* --------------------------------________---- 14MHz DTACK* DLATCH ________________________________--------____ Data Latch OK, keep in mind this is just a rough sketch. You have two worlds operating here, 7MHz and 14MHz. Anytime an access to the main Amiga bus happens, you have to translate 14MHz cycles into 7MHz equivalent cycles. This is just one way, basically the way the A26x0 and A3000 handle it. First of all, you have to sync the 14MHz address strobe up to the 7MHz clock. As long as you're synchronous, ASEN* can be some kind of flip-flop that samples AS* on the rising edge of the 7MHz clock. AS* may be nothing more than this output driven through a tristatable buffer of some kind, or it may get more complex as necessary. Anyway, once AS* goes out, you have defined S2. You have to ignore DTACK* completely until 7MHz S4. From thereon, you sample it on the falling edge; when you actually have DTACK* on that sample edge, you have found the edge between S4 and S5. The next falling edge, S6/S7, is where data on the 68000 bus must be latched. I wait until the data is actually latched before DTACK*ing the faster CPU, but you don't actually have to wait that long in a synchronous-clock system, you just have to insure that the latched data is valid one clock after the 14MHz 68000 recognizes its DTACK*. Note that, once 7MHz AS* is negated (sometime during S7), you once again will ignore 7MHz DTACK until S4/S5 of the next cycle comes around. -- Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy "That's me in the corner, that's me in the spotlight" -R.E.M.