fillmore@SUN2.EMR.CA (Bob Fillmore) (04/18/91)
In article <20298@cbmvax.commodore.com> daveh@cbmvax.commodore.com (Dave Haynie) writes: > >Specific to the Amiga, there were several problems. First of all, the video >chips are directly tied to video. If you speed up the bus cycle, you speed >up the video shift rate, unless you go to a multiple of it. The current Agnus >runs a 280ns cycle. To double that, and go to 140ns, you would need 60ns >DRAM, which are only now becoming available in large quantities, and are still >quite expensive (though, if they're on schedule, they'll get cheap in the next >year or so). Any somewhat faster bus speedup and you lose NTSC or VGA scan >and pixel rates. While it's conceivable that you could divorce the scan >rate from the bus rate, that's a MAJOR architectural change, far more complex >than building new chips that speed up in other ways (32 bit bus is the way >the microprocessors gained their modern speed, more than clock rate speedups). > >-- >Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests" > {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy > "That's me in the corner, that's me in the spotlight" -R.E.M. A question I have been meaning to ask for a while: How hard would it be to implement phased memory banks in the Amiga, a technique used by mainframe manufacturers to implement fast memory by using slow DRAM chips? Phased memory banks work by using the low-order bits of the address as a bank select so that the address bus cycle can be faster than the memory bank cycle. ________________________ Bob Fillmore, Systems Software & Communications email: fillmore@emr1.emr.ca Computer Services Centre, BIX: bfillmore Energy, Mines, & Resources Canada Voice: (613) 992-2832 588 Booth St., Ottawa, Ontario, Canada K1A 0E4 FAX: (613) 996-2953
aduncan@rhea.trl.oz (Allan Duncan) (04/18/91)
In article <20298@cbmvax.commodore.com> daveh@cbmvax.commodore.com (Dave Haynie) writes: >Specific to the Amiga, there were several problems. First of all, the video >chips are directly tied to video. If you speed up the bus cycle, you speed >up the video shift rate, unless you go to a multiple of it. The current Agnus >runs a 280ns cycle. To double that, and go to 140ns, you would need 60ns >DRAM, which are only now becoming available in large quantities, and are still >quite expensive (though, if they're on schedule, they'll get cheap in the next >year or so). Any somewhat faster bus speedup and you lose NTSC or VGA scan >and pixel rates. While it's conceivable that you could divorce the scan >rate from the bus rate, that's a MAJOR architectural change, far more complex >than building new chips that speed up in other ways (32 bit bus is the way >the microprocessors gained their modern speed, more than clock rate speedups). I would have thought that _full_ 32 bit chips would also allow equivalent 140ns operation while keeping Dram speed down - isn't the 3000 variant halfway to this? Allan Duncan ACSnet a.duncan@trl.oz (+613) 541 6708 ARPA a.duncan%trl.oz.au@uunet.uu.net UUCP {uunet,hplabs,ukc}!munnari!trl.oz.au!a.duncan Telecom Research Labs, PO Box 249, Clayton, Victoria, 3168, Australia.
daveh@cbmvax.commodore.com (Dave Haynie) (04/20/91)
In article <9104172234.AA04604@sun2.emr.ca> fillmore@SUN2.EMR.CA (Bob Fillmore) writes: >In article <20298@cbmvax.commodore.com> daveh@cbmvax.commodore.com (Dave Haynie) writes: >A question I have been meaning to ask for a while: >How hard would it be to implement phased memory banks in the Amiga, >a technique used by mainframe manufacturers to implement fast memory >by using slow DRAM chips? That's pretty common in microcomputers too, within reason. Most of the implementations I've seen keep the bank number to two, since in modern memories TRP < TRAS. The main problem is the increase in memory controller size. You typically need a set of data buffers, separate addresses, RAS*, and CAS* lines for each bank. What this technique does, for those unfamiliar with it, is hide the row precharge time for each bank of memory, most of the time, since you have a real good chance of alternating between banks for each memory access. You basically get DRAM that runs limited by access time rather than by cycle time. This can be significant -- for example, a 100ns DRAM typically have a 190ns cycle time. However, unless you can build the system to account for consecutive access to the same bank, you're in trouble, because its impossible to guarantee, at least in most systems, that the banks will always alternate. Most CPU systems can easily adjust dynamically to memory speed by inserting wait states. Amiga chips, on the other hand, can't -- they're exactly slaved to run certain memory cycles during certain "slots" in the video scan, and can't handle any memory wait at all. That's not to say some bank interleave scheme couldn't work. It is a perfectly valid way to generally speed up operation, though also a bit expensive in the pincount area for an already tight Amiga system chip. >Bob Fillmore, Systems Software & Communications email: fillmore@emr1.emr.ca -- Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy "That's me in the corner, that's me in the spotlight" -R.E.M.