nick@bilpin.UUCP (nick) (09/21/90)
NCR today announced the PMCVI (25MHz MC68040) upgrade for 32/500 and 32/700 systems. I gather that the performance improvement is significant over the 030 models. The figures that I have based on the Neal Nelson benchmarks (in fact a geometric mean using a 32/650 w SMSC as 1.00) are as follows: Model Controller NN perf 32/650 SMSC 1.00 32/500 HPMSC 1.50 32/700 HPMSC 2.60 32/750 on board SCSI 5.20 Although I am reliably informed that the PMCVI is now coming in at about 6.00 which is a significant improvement. The information I have mentions a new memory system which allows for burst mode writes as well as reads. I have the following questions: 1.How much does this new memory design contribute to the overall speed up, ie what are the figures for a PMCVI without the new memory design as per a stock 32/700 upgrade ? 2.What caching strategy does the PMCVI uses ? 3 Is this upgrade just be a board swap, or will I have a new OS release to install as well ? NCR also announced the AP3 for the 32/8X0 systems which uses the same 25MHz MC68040 part as the PMCVI. I have generally found that the bottleneck on the 32/8X0 when used for typical database applications (my interest) is the MultiBusII which becomes saturated with shared memory operations. ie 6 APII's do not significantly improve performance over 2 APII's on certain benchmarks which I have run. If this is still the case with the AP3 how much real performance improvment can we expect from the new processor, or will NCR re design the shared memory architecture to free up the bus and let the 040's fly ? Nick -- _______________________________________________________________________________ Nick Price SRL Data || Apple link : UK0001 1 Perren Street London NW5 3ED || UUCP : nick@bilpin.uucp Phone: +44 1 485 6665 || Path : nick@bilpin.co.uk