harris@sauron.Columbia.NCR.COM (Ray Harris) (04/16/91)
-In article <391@wybbs.mi.org> sleepy@wybbs.UUCP (Mike Faber) writes: ->In article <5904@holston.UUCP> barton@holston.UUCP (Barton A. Fisk) writes: ->>In article <nolan.670834286@helios> nolan@helios.unl.edu writes: ->> ->>Do the high end (ie. 3400 and >) support symetric multiprocessing? -> ->This was one thing that NCR was VERy vague about. They're going to use ->(they say) loosely coupled processing, and the 3700 and 3800 are suppposed to ->supercede all supercomputers in terms of MIPS. The lowest level 3000 that is ->multi processor - the 3500 - uses tightly coupled architechture, and will ->use up to 6 486/50's. ->> The MP 3400 and 3500 models will be tightly coupled and symmetric. The 3550 will support up to eight 50 Mhz 80486's. -- Ray.Harris@ncrcae.Columbia.NCR.COM (Ray Harris) ..!uunet!ncrlnk!ncrcae!harris ...!gatech!hubcap!ncrcae!harris
barton@holston.UUCP (Barton A. Fisk) (04/20/91)
In article <697@ncrsea.Seattle.NCR.COM> dmdc@ncrsea.Seattle.NCR.COM (Dennis M. Dooley) writes: >In article <391@wybbs.mi.org> sleepy@wybbs.UUCP (Mike Faber) writes: >>In article <5904@holston.UUCP> barton@holston.UUCP (Barton A. Fisk) writes: >>>In article <nolan.670834286@helios> nolan@helios.unl.edu writes: >>> >>>Do the high end (ie. 3400 and >) support symetric multiprocessing? >> [NCR 3000 info deleted] What bus is NCR going to go with on the high end 486/50 systems? Proprietary buses tend to fly in the face of open systems in my opinion. Maybe someone could comment on whether the MC bus will handle multiple processors? Or is NCR thinking about EISA? I read a comment by an NCR marketing spokesman in PW where he stated that one of the targets was the Systempro. -- uucp: holston!barton pseudo: barton@holston.UUCP
jlodman@beowulf.ucsd.edu (Michael Lodman) (04/21/91)
In article <5907@holston.UUCP> barton@holston.UUCP (Barton A. Fisk) writes: >What bus is NCR going to go with on the high end 486/50 systems? In the level 7, it is my understanding that the processor-memory interface will be a proprietary very wide (128 bit) bus. I/O will be handled through various optional attached buses, including MC and MBII. I don't know how many processors NCR will be placing in a single cabinet of the level 7, but my (somewhat educated) guess is 4-8. These separate cabinets will be interconnected through a new verion of the Teradata Y-Net being specifically developed for this product and referred to as the BY-Net (I think "B" stands for "Big", but I'm just guessing). Thus, the thousands of processors referred to by NCR will be attached through the BY-Net. >Proprietary buses tend to fly in the face of open systems in my >opinion. Depending on what buses you are referring to, I agree. Unfortunately, there isn't a standard bus available which supports the transfer bandwidth between processors and memory which NCR needs to sustain in the level 7. The I/O buses will be completely industry standard, except that NCR may choose to support some of their older proprietary I/O standards as well to bring customers over to the new system. >Maybe someone could comment on whether the MC bus will handle >multiple processors? Or is NCR thinking about EISA? I read a >comment by an NCR marketing spokesman in PW where he stated that >one of the targets was the Systempro. The MC bus will handle multiple processors. I really doubt that anyone would want to hang memory off it as well, though. I don't think NCR has EISA plans, but my information could well be dated. I would appreciate any corrections if I am incorrect in my understanding of the level 7. -- Michael Lodman Department of Computer Science Engineering University of California, San Diego jlodman@cs.ucsd.edu (619) 672-1673