mark@mips.COM (Mark G. Johnson) (10/23/90)
>I was there, and what I heard was: > a) The speaker (Keith Diefendorff), and the foils, said > "The following is not a product announcement but rather > a disclosure of Motorola's plans for the 88000 Family > and a sneak preview of the next generation processor." > > .... > >The foils say 3-5X performance increase over 88100/88200, using >0.8micron TLM HCMOS, less than 1.5M transistors. Especially interesting >are the "80-bit wide internal data paths" (For FP), and other features I for one am willing to bet $0.75, or the price of a 12oz. Coke Classic (whichever amount is larger :-), that on the day when the 88110 die photo is officially released, the chip will NOT have triple level metel HCMOS processing. Another 75cents says that on the day when the 88110 die photo is officially released, Motorola will not be building _any_ of its 32-bit microprocessors, RISC or CISC, 88k or 68k, using triple level metal CMOS processing. I'll also bet 50 cents that the first merchant RISC microprocessor using CMOS transistors and triple level metal processing, will be from Texas Instruments. There's already been a Hewlett Packard Precision RISC in TLM CMOS; if that counts as merchant then I've already lost the 50 cents (to myself :-). Finally, I'll stretch my resources to the limit and bet a whopping 15 cents that when you run 100x100 DP Linpack on a system using the 88110 (say, a future Aviion), the results will not be bit-for-bit identical with the previous 88100-based systems (say, the current Aviion). This is only a wild guess based upon the use of 80b internal arithmetic in Moto's 68882 and other existing chips that have 80b internal data paths. I don't presume to guess which of the two answers would be "more accurate", just that they are not identical. -- -- Mark Johnson MIPS Computer Systems, 930 E. Arques M/S 2-02, Sunnyvale, CA 94086 (408) 524-8308 mark@mips.com {or ...!decwrl!mips!mark}
billm@oakhill.UUCP (Bill Moyer) (10/24/90)
In article <42312@mips.mips.COM> mark@mips.COM (Mark G. Johnson) writes: >I for one am willing to bet $0.75, or the price of a 12oz. Coke Classic >(whichever amount is larger :-), that on the day when the 88110 die >photo is officially released, the chip will NOT have triple level metel >HCMOS processing. Another 75cents says that on the day when the 88110 >die photo is officially released, Motorola will not be building _any_ >of its 32-bit microprocessors, RISC or CISC, 88k or 68k, using triple >level metal CMOS processing. I'll also bet 50 cents that the first >merchant RISC microprocessor using CMOS transistors and triple level >metal processing, will be from Texas Instruments. There's already been >a Hewlett Packard Precision RISC in TLM CMOS; if that counts as merchant >then I've already lost the 50 cents (to myself :-). > >Finally, I'll stretch my resources to the limit and bet a whopping >15 cents that when you run 100x100 DP Linpack on a system using the >88110 (say, a future Aviion), the results will not be bit-for-bit >identical with the previous 88100-based systems (say, the current >Aviion). > -- Mark Johnson > MIPS Computer Systems, 930 E. Arques M/S 2-02, Sunnyvale, CA 94086 > (408) 524-8308 mark@mips.com {or ...!decwrl!mips!mark} you're on for the first two bets. I won't comment on the third. As for the fourth, IEEE compliance means just that. I'm willing to bet that bit identical results will not be guaranteed with any given chip/system (R2000/3000,SPARC,88K) if the compiler is allowed to reorder code for optimization purposes. Bill Moyer Motorola, Inc. ...!oakhill!billm
shebanow@oakhill.UUCP (Mike Shebanow) (10/24/90)
In article <42312@mips.mips.COM> mark@mips.COM (Mark G. Johnson) writes: >I for one am willing to bet $0.75, or the price of a 12oz. Coke Classic Only $0.75? :-) (Also, some of us here are Pepsi fans) With these high stakes, your confidence in your sources is incredible. Mike Shebanow 88K Product Development ----------------------------------- Disclaimer: I speak only for myself.