robertb@cs.washington.edu (Robert Bedichek) (05/07/91)
I know of one system that runs at 20 MHz that fills a cache line in 9 cycles. I doubt anyone goes faster than 6 cycles. I believe that the early Aviions took 16 cycles. I am designing a multiprocessor based on the 88k Hypermodule and I am trying to make the memory as fast as possible. It would be helpful to me to know what other designers have been able to achieve. Memory system performance is the limiting factor, I think, for 88k systems with more than one CPU on almost any problem. The number of cycles it takes to fill or write out a cache line is critical. Here is a table of the number of cycles for a cache line fill and the peak memory system bandwidth: cycles memory system bandwidth for a 25 MHz 88k --------------------------------------------------- 5 80 6 67 7 57 8 50 9 44 10 40 11 36 A little background: my 88ks will run at 25 MHz and I will use 80ns DRAM SIMMs. Since I am using Hypermodules, I will have up to four CPUs and eight CMMUs. This means that the M-Bus will have about 130pf of load per line. Currently, my design has two banks of DRAMs so that once the first word is ready, the rest will come out one per cycle. I can get the first word of a read out in three 40ns cycles, which give a 7 cycle total (1 for address, three for first word, three for the next three words). If the next access follows immediately and is to the same bank, there will be an extra cycle to allow for precharging. So sometimes it will take 7 cycles and sometimes 8 to fill a cache line. The timing for writes is a little easier, I think I can do it in 6 cycles, plus an extra cycle for precharging if the next access follows immediately and is to the same bank as the previous access. My questions: 1. Is there a fundamental problem with doing this at 25 MHz with 80ns DRAMs? 2. What is the fastest memory system that uses DRAMs that has been built to date for the 88k? 3. Can anyone venture a guess as to when Motorola will sell Hypermodules with the new 88204 CMMU? 4. Has anyone built a 5 cycle memory system for the 88k? If so, what was the clock period? How fast and how large were the SRAMs? 5. Can anyone gues when the 88100 will be available and what speed Moto is aiming for? 6. Has anyone designed an 88k system that uses S-Bus? (S-Bus is the bus that Sparcstations use.) Robert Bedichek robertb@cs.washington.edu