larryh@tekgvs.LABS.TEK.COM (Larry Hutchinson) (11/07/89)
In article <36198@apple.Apple.COM> noah@Apple.COM (Noah Price) writes: >In article <6283@tekgvs.LABS.TEK.COM> larryh@tekgvs.LABS.TEK.COM (Larry Hutchinson) writes: >>Noah Price of Apple confirmed my suspicions that the IIci is running two >>wait states and that the SE/30 etc. runs one wait state. > >Actually, the IIci runs three wait states for random reads, since they're now >synchronous which means a zero wait state random read would be 2 clocks. Sorry about that. I was trying to keep the comparison between the IIcx and the IIci simple -- perhaps too simple. The bottom line is that the IIci takes an extra cycle for reads relative to the IIcx (same as SE/30, IIx). Noah: Why does the IIci use synchronous access? To improve the cache performance perhaps? What is the situation with a chache board installed? >It's not quite that easy though, since the IIci does burst reads into the >on-chip cache which are 5 clocks for the first longword access, followed three >2 clock accesses for the other three long words in the burst. The '030 user's manual says "The data burst enable bit must be set to enable burst filling of the data cache." Anyone know if this bit is set when running user code? Larry Hutchinson, Tektronix, Inc. PO Box 500, MS 50-383, Beaverton, OR 97077 UUCP: [uunet|ucbvax|decvax|hplabs]!tektronix!tekgvs!larryh ARPA: larryh%tekgvs.LABS.TEK.COM@RELAY.CS.NET CSNet: larryh@tekgvs.LABS.TEK.COM
noah@Apple.COM (Noah Price) (11/07/89)
In article <6303@tekgvs.LABS.TEK.COM> larryh@tekgvs.LABS.TEK.COM (Larry Hutchinson) writes: >The '030 user's manual says "The data burst enable bit must be set to >enable burst filling of the data cache." > >Anyone know if this bit is set when running user code? Yes, both the data and instruction caches are enabled and burst enabled during the boot process. noah ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ noah@apple.com Mac IIci Hardware Design Team ..!{sun,decwrl}!apple!noah Apple Computer, Inc.
daveh@cbmvax.UUCP (Dave Haynie) (11/08/89)
in article <6303@tekgvs.LABS.TEK.COM>, larryh@tekgvs.LABS.TEK.COM (Larry Hutchinson) says: > why does the iici use synchronous access? to improve the cache performance perhaps? synchronous cycle mode is required for burst cache fills. most '030 systems that support burst fills always use synchronous mode, simply because, once you fulfill the requirements for burst mode, you work with synchronous mode regardless of whether you're actually bursting or not. there are two other reasons for using synchronous mode (other than for burst support). the most obvious is that synchronous cycles are a minimum of two clocks, versus three for asynchronous cycles. the other reason is that synchronous cycles are terminated 1/2 clock later, so if you're waiting for a termination from something, there may be less lag with the synchronous mode (though the synchronous cycle termination must obey proper setup and hold times to the 68030, while the asynchronous signals can come in at any time). > Larry Hutchinson, Tektronix, Inc. PO Box 500, MS 50-383, Beaverton, OR 97077 -- Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy Too much of everything is just enough