pj@pnet51.orb.mn.org (Paul Jacoby) (11/12/89)
Noah@apple.com writes: >>Yes, both the data and instruction caches are enabled and burst enabled during the boot process. << So I assume that Jim Hamilton's "CacheControl" cdev just goes out to the chip and resets the appropriate bit(s) to disable or re-enable the cache(s)? Another question: Are there any stats on how often the '030 Macs are able to utilize burst mode? .-----------------------------------------------------------------------------. | UUCP: {rosevax, crash, orator}!orbit!pnet51!pj | Working with idiots keeps | | ARPA: crash!orbit!pnet51!pj@nosc.mil | my life interesting... | | INET: pj@pnet51.cts.com | | `-----------------------------------------------------------------------------'