leovm@cs.vu.nl (Leo van Moergestel) (02/05/90)
This is how a 68030 accesses memory if it uses asynchronous accessing method. ----| |----| |----| | | | | | |----| |----| |---- S0 S1 S2 S3 S4 S5 An asynchronous read Cycle without wait states takes 3 clockcycles (a total of 180 nsec. for a 16.7 MHz CPU). These read cycles are divided in 6 clock states (S0-S5) Address is valid 30 nsec. (maximum) after beginning of S0, Data must be valid 5 nsec. before the end of S4. This results in 30+30+30+25 = 115 nsec. If you add one waitcycle you can simply add a complete clockcycle to this amount -> 175 nsec. Even if you take in account overhead of address multiplexer and databusbuffer delay. This is not a problem for 120nsec DRAMs (SIMMs are dynamic RAMs). DRAM addressing is a little bit complex. You address it as a matrix, first you generate te row address, then the column address There are two address strobes on the chip RAS (Row Address Strobe) and CAS (guess). You need a multiplexer to accomplish this. The access time for a Dynamic ram chip is measured from the RAS signal to the data valid. For a 120 nsec this is of course lower or the same as 120 nsec. After accessing a chip it should be left alone for a while for an internal recover. The random cycle time for a 120 nsec. chip is 220 nsec or something like that. If you take a read cycle with one waitcycle the memory cycle time is 240 nsec. This is within the 120 nsec RAM chip specs. External logic generates a signal for the CPU that data is available. This signal is not generated by RAM. The CPU automatically inserts wait cycles if the logic tells the CPU there is no data yet. There are other readcycle schemes available but this one seems to be the most straightforward. For a write cycle you just have to take in account that the CPU is generating the data to be written. Leo van Moergestel Vrije Universiteit Amsterdam