tom@wcc.oz (Tom Evans) (03/01/90)
In article <9792@batcomputer.tn.cornell.edu>, gaarder@batcomputer.tn.cornell.edu (Steve Gaarder) writes: > > 1. The bit rate is given as 230.4 kbaud, and the clock input to the > SCC as 3.672 MHz. However, 16 times 230.4k comes out to 3.6864 MHz. > 3.672 should give a rate of 299.5 kbaud. What gives? ^^^^^ nope - 229.5k Apple use a 15.6672 MHz crystal (IM-III-18 and looking at a board). This is used by the video hardware which runs a screen that is 370 lines by 704 pixels (342 + 28 V Blank by 512 + 192 H Blank) bits wide (IM-III-18). This gives a frame rate of 60.147 Hz (you thought it was 60?). Now the obvious choice for the SCC clock is to divide the 15.6672MHz by 4. This gives 3.9168 MHz which is too high - it should be 3.6864MHz to be 230,400 * 16 (as noted by Steve). The SCC signal is ACTUALLY the 15.6672 MHz clock divided by 15/64 courtesy of the TSG chip. This gives 3.672 MHz as stated in IM-III-25. This gives a LocalTalk speed of 3.672/16 = 229,500 Hz, which is 99.6% of the specified speed. 0.4% is very close. The SCC has a digital phase-lock-loop in it so it can handle a speed variation far wider than this. If you wnat to know how to get 15/64'th of something, use a CRO like I did :-). --------- Tom Evans tom@wcc.oz.au | Webster Computer Corp P/L | "The concept of my 1270 Ferntree Gully Rd | existence is an Scoresby, Melbourne 3179 | approximation" Victoria, Australia | 61-3-764-1100 FAX ...764-1179 | D. Conway 2109 O'Toole Avenue, Suite J SAN JOSE CA 95131 - 1303 CALIFORNIA 1-408-954-8054 FAX 1-408-954-1832