grobbins@grad1.cis.upenn.edu (04/13/90)
The March issue of Apple Direct (a developer magazine) includes a block diagram of the IIfx hardware. The diagram shows the system divided up into a fast section, including the 40 MHz 68030, RAM, ROM, and cache, and a slow section, with the SCSI, ADB, and other I/O devices connected to a separate pair of address and data lines. A set of fast/slow buffers sits between the sections. The diagram puts the 40 MHz 68882 math coprocessor on the slow side of the buffers. Is this a drawing mistake, or does the coprocessor really belong on that side? Shouldn't the coprocessor be at least as tightly coupled to the '030 as the RAM, considering that it is also (labeled as) being run at 40 MHz? Grobbins grobbins@eniac.seas.upenn.edu