dhoyt@vx.acs.umn.edu (DAVID HOYT) (12/18/90)
Although most macs can get by with a mix of memory simms at different speeds
it can cause problems if you mix the chips within the same bank. Imagine you
have a chip that is rated at 120ns with a 120ns driver. (Greatly simplifying)
you will have a signal that looks like this
+---+ +---+
| | | |
----+ +-----------------------+ +----------------------
0 ns Time-> 120ns
I.e. the amount of time that the signal takes to get through the chip is
roughly 120ns. Now with a chip rated at 60ns running at 60ns the signal
will take 60ns to pass through the chip. All well and good. But now
take the 60ns chip and run it at 120ns. The chip is still designed so that
the signal will take 60ns to clear the chip. You'll end up with at situation
like
+---+ +---+
| | | |
----+ +--------------+ +----------------------
0 ns Time-> 120ns
Now most memory speeds are not exact. A chip nominally rated at 120ns
may actually be usable at 110ns. Because of this, when the engineers design a
system they allow for some amount of skew. For this reason, you can often get
by with mixing and matching chips. But you can also get bit if the skew is too
much. Which is why apple suggests using the same speed chips.
On the macs with two lines (banks) of memory there are two drivers, one for
each bank. With different drivers, the skew between banks is much less
important than skew within banks. This is why the rule of thumb is 'use the
same speed within banks' rather than 'use the same speed for all chips.'
Now this is all a gross generalization and the real world is much more
complex, but hopefully this will give some idea why it's a bad idea to
mix-and-match willy-nilly.
david | dhoyt@vx.acs.umn.edu | dhoyt@umnacvx.bitnetamanda@visix.com (Amanda Walker) (12/19/90)
All right, now I'm really confused, and I've built DRAM circuitry... In article <2915@ux.acs.umn.edu> dhoyt@vx.acs.umn.edu writes: >Imagine you have a chip that is rated at 120ns with a 120ns driver. >(Greatly simplifying) you will have a signal that looks like this > +---+ +---+ > | | | | > ----+ +-----------------------+ +---------------------- > 0 ns Time-> 120ns > >I.e. the amount of time that the signal takes to get through the chip is >roughly 120ns. Not even close. There is no signal "going through the chip." The "speed" of a dynamic RAM which is usually quoted (and which is printed on the chip) is not a propagation delay. It is the Row Access Time, usually abbreviated Trac, and refers to the guaranteed maximum time it will take for the data outputs to become stable, or the data inputs to be properly latched, after the Row Address Strobe (RAS) is asserted. In simple terms, this is how long you have to wait before looking at the outputs to be sure they are stable. They will actually become stable at some time before that, but until RAS is negated, the outputs will just sit there. The length of the RAS pulse is a function of the memory addressing circuitry (in this case, the Mac), not of the SIMM. There are no strobes or other signals generated by the DRAMs, besides the data bits themselves, and those data bits are held on the bus until the Mac tells the chip to let go, as it were. Once again, the Mac can't tell when the data is ready; it just waits the rated amount of time and latches the data then. If the outputs settle 20ns early, it doesn't care. They'll still be there until it gets done with them. >Now this is all a gross generalization and the real world is much more >complex, Indeed. >but hopefully this will give some idea why it's a bad idea to >mix-and-match willy-nilly. Nope. Sigh. I have no idea what you're talking about, but it sure isn't DRAM. I still want to hear an explanation that's either quoted from the tech note or straight from one of the hardware dudes who designed the memory system in question. I mean, I don't even know how to build a dynamic memory subsystem that could tell the difference, even on purpose... I've even got a IIsi at home--I'll see if I can scrape up some mixed-speed SIMMs and actually try this out. -- Amanda Walker amanda@visix.com Visix Software Inc. ...!uunet!visix!amanda -- "Generally you don't see that type of behavior in a major appliance." --Ghostbusters
dhoyt@vx.acs.umn.edu (DAVID HOYT) (12/20/90)
In article <NBMNdxye@visix.com>, amanda@visix.com (Amanda Walker) writes... >Nope. Sigh. I have no idea what you're talking about, but it sure >isn't DRAM. Well, yes and no. I realize that there is no 'signal' that goes through the chip. I used that 'simplification' as a way of explaining what is really going on, but that is not really goes on. Think of a straight wire with zero impedance. A signal will travel through it at a rate of about 30cm/ns. Boost the impedance on the wire and the signal take longer to travel the same distance. The same thing happens with memory chips. The lower speed ones tend to have higher impedances. The higher speed chip will have it's downbeat a bit before the slower chip. In micros there are fairly few components and the memory drivers are fairly simple; so using different speed chips usually are not a problem as long as the speeds are fairly close. In a more complex system, such as a mainframe, all of the small differences in speed could add up to a big difference in the end. With the end result of the computer not working. This is why mainframe computer engineers specify both the best and the worst behavior allowable to their chip suppliers. With micros, because of the reduced complexity, you can get away with a little bit more slack at either end. But you can still run into problems. If you put 4ns memory in your mac most likely it wouldn't work. The advice of Apple is sound. Don't mix if you don't have to mix. And if you do mix, don't mix in the same bank. david | dhoyt@vx.acs.umn.edu | dhoyt@umnacvx.bitnet Worry about it a little bit, but that's all. -- John Hartford
n67786@lehtori.tut.fi (Nieminen Tero) (12/20/90)
In article <NCrwEGxa@visix.com> amanda@visix.com (Amanda Walker) writes: In article <2924@ux.acs.umn.edu> dhoyt@vx.acs.umn.edu writes: >The lower speed ones tend to have higher impedances. The higher speed >chip will have it's downbeat a bit before the slower chip. So far I follow you; I have in fact run into some weird speed problems (for example, mixing FAST and LSTTL chips), and I can see the possibility that using memory that is a whole lot faster than the design could cause a problem. However, I still do not see how the speed of one SIMM can affect the others in its bank, even with brain-dead driver circuitry. I mean, if using all 100ns works, and using all 80ns works, how can using two of each cause a problem. All of the SIMMs are still within tolerances--just in different places within them. Only reason for this I can think of is that the logic doesn't properly check the memory ready lines from all simms in a bank but instead just uses one single sim for that purpose. Now if the simm in question happens to be faster than the others in the bank the other simms might not be staedy at the time the cpu issues the read. This all comes down to the gray areas in signal timing charts, ie. transition periods. If mixing different speed simms cause the signals to fall out of those areas you may be in trouble. The timings (and the ram chip speeds also) are probably designed so that this should not be a problem within same speed chips. Amanda Walker amanda@visix.com Visix Software Inc. ...!uunet!visix!amanda -- Tero Nieminen Tampere University of Technology n67786@cc.tut.fi Tampere, Finland, Europe
amanda@visix.com (Amanda Walker) (12/21/90)
In article <2924@ux.acs.umn.edu> dhoyt@vx.acs.umn.edu writes: >The lower speed ones tend to have higher impedances. The higher speed >chip will have it's downbeat a bit before the slower chip. So far I follow you; I have in fact run into some weird speed problems (for example, mixing FAST and LSTTL chips), and I can see the possibility that using memory that is a whole lot faster than the design could cause a problem. However, I still do not see how the speed of one SIMM can affect the others in its bank, even with brain-dead driver circuitry. I mean, if using all 100ns works, and using all 80ns works, how can using two of each cause a problem. All of the SIMMs are still within tolerances--just in different places within them. >If you put 4ns memory in your mac most likely it wouldn't work. The advice of >Apple is sound. Don't mix if you don't have to mix. And if you do mix, don't >mix in the same bank. We're not talking putting bipolar SIMMs (an amusing concept) into a IIsi. We're talking about putting in SIMMs that fall into different spots in the "safe zone." If the problem really was speed slew of some sort, you'd have to have actual matched sets of SIMMs, not just ones all stamped with the same speed. A 100ns SIMM may well be an 80ns SIMM that got marked as 100ns because the memory company had more orders for 100ns SIMMs that month. The rating is simply the worst case--the best case is always undefined. -- Amanda Walker amanda@visix.com Visix Software Inc. ...!uunet!visix!amanda -- "I wouldn't be surprised if the architecture of Intel's microprocessors were eventually linked to the eventual fall of mankind." --Steve Gibson
dhoyt@vx.acs.umn.edu (DAVID HOYT) (12/21/90)
In article <NCrwEGxa@visix.com>, amanda@visix.com (Amanda Walker) writes... > However, I still do not see how the speed of one SIMM can >affect the others in its bank, even with brain-dead driver circuitry. >I mean, if using all 100ns works, and using all 80ns works, how can >using two of each cause a problem. All of the SIMMs are still within >tolerances--just in different places within them. It's a matter of how much difference in speed (and other electrical) differences the memory drivers can handle. Each chip is unlikely to have exactly the same characteristics as the other chips. Memory drivers are designed to compensate for these differences as long as they are small. Now each bank of memory has its own driver circuitry, so each bank can handle separate ranges of variations (++++ vs ----). Variation between banks is then adjusted so the entire memory subsystem looks to be the same. This is why you can get by with a bit more differences between banks than within banks. >We're not talking putting bipolar SIMMs (an amusing concept) into a IIsi. Okay, so I cheated. Bipolar chips would either be blown by or blow the memory drivers. > A 100ns SIMM may well be an 80ns SIMM that got marked >as 100ns because the memory company had more orders for 100ns SIMMs that >month. The rating is simply the worst case--the best case is always >undefined. In the micro market place the best case might be undefined (because nobody knows to ask) but the real world the best case is designated as well. When Cray builds a 256 Megaword (call it 2GB in the micro world) Cray 2 you better believe that it specifies both the best and the worst case for those chips. If the memory supplier 'slipped' in a few 60ns chips along with the trainload of 80ns chips it could render the $20 million machine useless. It would probably cause sporadic memory errors at the very best. The reason that we can get by with it in our micros is that the micros don't have the complexity that turns lots of little differences into one big, unworkable difference. david | dhoyt@vx.acs.umn.edu | dhoyt@vx.acs.umn.edu
kaufman@Neon.Stanford.EDU (Marc T. Kaufman) (12/21/90)
In article <N67786.90Dec20162530@lehtori.tut.fi> n67786@lehtori.tut.fi (Nieminen Tero) writes: >Only reason for this I can think of is that the logic doesn't properly >check the memory ready lines from all simms in a bank but instead just >uses one single sim for that purpose... That would be a good argument, IF there were "memory-ready" lines from the simms... but there are no such lines. Simm timing is strictly controlled by external circuitry waiting for the prescribed times. Tell me, how did you think of that reason? What data book or hardware reference has it? Marc Kaufman (kaufman@Neon.stanford.edu)
amanda@visix.com (Amanda Walker) (12/22/90)
In article <N67786.90Dec20162530@lehtori.tut.fi> n67786@lehtori.tut.fi (Nieminen Tero) writes: >Only reason for this I can think of is that the logic doesn't properly >check the memory ready lines from all simms in a bank but instead just >uses one single sim for that purpose. This would be a perfect explanation except for one problem: SIMMs don't have "memory ready" lines, or any kind of strobe or signal that indicates when the data is ready. It's the driver circuit's responsibility to wait long enough. This is why, for example, you can't use cheaper but slower SIMMs than a machine is rated for--the driver logic will assume the data is ready, even if it's not, because there is no way for it to tell. -- Amanda Walker amanda@visix.com Visix Software Inc. ...!uunet!visix!amanda -- Black holes are where God is dividing by zero.
peirce@outpost.UUCP (Michael Peirce) (12/22/90)
In article <NCrwEGxa@visix.com>, amanda@visix.com (Amanda Walker) writes: We're not talking putting bipolar SIMMs (an amusing concept) into a IIsi. > We're talking about putting in SIMMs that fall into different spots in > the "safe zone." If the problem really was speed slew of some sort, > you'd have to have actual matched sets of SIMMs, not just ones all stamped > with the same speed. A 100ns SIMM may well be an 80ns SIMM that got marked > as 100ns because the memory company had more orders for 100ns SIMMs that > month. The rating is simply the worst case--the best case is always > undefined. This is exactly how they do it. Each production line has a big test machine at the end. They sort the chips into various bins based on their conclusion that this chip will have its outputs settle in 80ns or 100ns. Many many times they will label all the chips that tested at a faster speed with the lower speed just because of the orders coming in that week. Many chips labeled 100ns are in fact the very same chips that tested as 80ns and could have been labeled as such. -- michael, (very) formerly of Fairchild Test Systems -- Michael Peirce -- {apple,decwrl}!claris!outpost!peirce -- Peirce Software -- Suite 301, 719 Hibiscus Place -- Macintosh Programming -- San Jose, California 95117 -- & Consulting -- (408) 244-6554, AppleLink: PEIRCE
amanda@visix.com (Amanda Walker) (12/22/90)
In article <2946@ux.acs.umn.edu> dhoyt@vx.acs.umn.edu writes: >It's a matter of how much difference in speed (and other electrical) >differences the memory drivers can handle. Can you give a detailed example of these differences? I still can't come up with any relevant differences that come into play only in combinations of dissimilar SIMMs. I mean, if we were talking about asynchronous memory subsystems, you might have a good point. However, we're talking quite vanilla dynamic RAM subsystems, which in my experience just don't act in the ways you seem to be claiming they do. This experience includes designing and building DRAM subsystems, as well as actually using mixed-speed SIMM banks in a Mac II without any mishap whatsoever. >Variation between banks is then >adjusted so the entire memory subsystem looks to be the same. "Adjusted?" What do you mean? The Mac memory circuitry, and any other conventional DRAM support logic, does not and cannot do any dynamic adaptation to the speed of the memory, since, as I have said before, It has no way to tell what that speed is. DRAM signal sequencing does not involve any feedback from the memory itself. Even memory support logic that has been designed to handle different speeds of memory has to be explicitly configured (via jumpers or something similar) for the appropriate speed. >In the micro market place the best case might be undefined (because nobody >knows to ask) but the real world the best case is designated as well. Since the IIsi is part of the micro marketplace, and was designed to use mass market memory, Cray memory design contraints are pretty irrelevant, wouldn't you say? Look, as I said before, I'm not trying to argue with reality, it's just that this "same-speed" claim contradicts both my own experience and my understanding of dynamic RAM technology, which so far has served me in very good stead... -- Amanda Walker amanda@visix.com Visix Software Inc. ...!uunet!visix!amanda -- "Furious activity is no substitute for understanding." --H. H. Williams
n67786@lehtori.tut.fi (Nieminen Tero) (12/23/90)
In article <NCKE4o6m@visix.com> amanda@visix.com (Amanda Walker) writes: In article <N67786.90Dec20162530@lehtori.tut.fi> n67786@lehtori.tut.fi (Nieminen Tero) writes: >Only reason for this I can think of is that the logic doesn't properly >check the memory ready lines from all simms in a bank but instead just >uses one single sim for that purpose. This would be a perfect explanation except for one problem: SIMMs don't have "memory ready" lines, or any kind of strobe or signal that indicates when the data is ready. It's the driver circuit's responsibility to wait long enough. This is why, for example, you can't use cheaper but slower SIMMs than a machine is rated for--the driver logic will assume the data is ready, even if it's not, because there is no way for it to tell. Ok. My knowledge was outdated to the times of static memories :). Thanks for the update. If this is the case one would appear to be playing russian roulette with fully loaded revolver, eh. Maybe the machines just have enough wait states to compensate.. BTW, it's often not possible to use slow rams on systems that have memory ready signal, cause the cpu don't know how to wait. -- Amanda Walker amanda@visix.com Visix Software Inc. ...!uunet!visix!amanda -- Black holes are where God is dividing by zero. -- Tero Nieminen Tampere University of Technology n67786@cc.tut.fi Tampere, Finland, Europe
kaufman@Neon.Stanford.EDU (Marc T. Kaufman) (12/24/90)
-(Nieminen Tero) writes: ->Only reason for this I can think of is that the logic doesn't properly ->check the memory ready lines from all simms in a bank but instead just ->uses one single sim for that purpose. >(Amanda Walker [one of many]) replies: > This would be a perfect explanation except for one problem: SIMMs > don't have "memory ready" lines, or any kind of strobe or signal that > indicates when the data is ready. ->then (Nieminen Tero) writes: ->Ok. My knowledge was outdated to the times of static memories :). Uh... Nieminen.... static memories don't have ready lines either. ->BTW, it's often not possible to use slow rams on systems that have ->memory ready signal, cause the cpu don't know how to wait. The only memory systems (not individual chips) I know of with "ready" lines are those interfaced to a bus structure, such as NuBus, VME or Versabus, etc. In all of these I am aware of, waiting for ready is a mandatory part of the bus protocol. Marc Kaufman (kaufman@Neon.stanford.edu)
sukenick@sci.ccny.cuny.edu (SYG) (12/25/90)
>memory support logic that has been designed to handle different speeds >of memory has to be explicitly configured (via jumpers or something >just that this "same-speed" claim contradicts both my own experience >and my understanding of dynamic RAM technology, which so far has Same with me. The other arguments for "same speed only" so far haven't convinced me. Can anyone come up with a convincing mechanism as to why mixed speed memory will not work? The memory speed only refers to time between select (or whatever signal) and when data is ready to be input or output. The only possible problem I could see with higher speed memory is their faster rise time which may introduce noise (or ring) for a board not designed for them...... But the speed difference is relatively small, so I would not think that this is a factor.
north@Apple.COM (Don North) (12/28/90)
In article <NBMNdxye@visix.com> amanda@visix.com (Amanda Walker) writes: >All right, now I'm really confused, and I've built DRAM circuitry... >In article <2915@ux.acs.umn.edu> dhoyt@vx.acs.umn.edu writes: >> >>Imagine you have a chip that is rated at 120ns with a 120ns driver. >>(Greatly simplifying) you will have a signal that looks like this >> +---+ +---+ >> | | | | >> ----+ +-----------------------+ +---------------------- >> 0 ns Time-> 120ns >> >>I.e. the amount of time that the signal takes to get through the chip is >>roughly 120ns. >> >Not even close. There is no signal "going through the chip." The >"speed" of a dynamic RAM which is usually quoted (and which is printed >on the chip) is not a propagation delay. It is the Row Access Time, > >Once again, the Mac can't tell when the data is ready; it just waits >the rated amount of time and latches the data then. If the outputs >settle 20ns early, it doesn't care. They'll still be there until it >gets done with them. Amanda is right; no if's and's or but's! There is no reason why SIMM speeds cannot be mixed as long as they meet the maximum access time spec'ed for the particular machine (ie, 120ns or 100ns or 80ns). Think about it; on a given SIMM there are EIGHT individual memory chips built from EIGHT individual pieces of silicon (they don't even have to be from the same manufacturer, but usually are) - those eight chips are certainly not matched down to the nearest nanosecond in their access times. In fact one could conceivably build a SIMM with a mixture of 80ns,100ns,120ns parts and call it a '120ns' SIMM. If TN176 says that SIMM speeds cannot be mixed then it is WRONG - as long as all the SIMMs meet or exceed (are faster) the required access time spec. I am intimately familiar with the various Mac memory interface circuits and have built numerous other DRAM controllers, and there is NO REASON why DRAM speeds cannot be mixed - as long as the required maximum access time is met. Remember, whenever you have more than ONE DRAM in a circuit you are mixing speeds! -- Don North ----- Apple Computer, Inc. ----- Advanced Technology Group UUCP: ...!{voder,nsc,decwrl,sun}!apple!north CSNET: north@Apple.COM {{ Facts are facts, but any opinions expressed are my own, and *do not* }} {{ represent any viewpoint, official or otherwise, of Apple Computer, Inc.}}
amanda@visix.com (Amanda Walker) (12/28/90)
In article <47604@apple.Apple.COM> north@Apple.COM (Don North) writes: >Amanda is right; no if's and's or but's! > ... >I am intimately familiar with the various Mac memory interface circuits and >have built numerous other DRAM controllers, and there is NO REASON why DRAM >speeds cannot be mixed - as long as the required maximum access time is met. >Remember, whenever you have more than ONE DRAM in a circuit you are mixing >speeds! Whew. Thank you, Don. I was beginning to wonder if I'd switched universes some time when I wasn't looking. Grin. Now, if people start arguing with *you*, I may suggest starting a new newsgroup called comp.sys.mac.folklore :)... -- Amanda Walker amanda@visix.com Visix Software Inc. ...!uunet!visix!amanda -- "I used to be disgusted; now I'm just amused." --Elvis Costello
Don.North@f20.n226.z1.FIDONET.ORG (Don North) (12/28/90)
Reply-To: north@Apple.COM In article <NBMNdxye@visix.com> amanda@visix.com (Amanda Walker) writes: >All right, now I'm really confused, and I've built DRAM circuitry... >In article <2915@ux.acs.umn.edu> dhoyt@vx.acs.umn.edu writes: >> >>Imagine you have a chip that is rated at 120ns with a 120ns driver. >>(Greatly simplifying) you will have a signal that looks like this >> +---+ +---+ >> I I I I >> ----+ +-----------------------+ +---------------------- >> 0 ns Time-> 120ns >> >>I.e. the amount of time that the signal takes to get through the chip is >>roughly 120ns. >> >Not even close. There is no signal "going through the chip." The >"speed" of a dynamic RAM which is usually quoted (and which is printed >on the chip) is not a propagation delay. It is the Row Access Time, > >Once again, the Mac can't tell when the data is ready; it just waits >the rated amount of time and latches the data then. If the outputs >settle 20ns early, it doesn't care. They'll still be there until it >gets done with them. Amanda is right; no if's and's or but's! There is no reason why SIMM speeds cannot be mixed as long as they meet the maximum access time spec'ed for the particular machine (ie, 120ns or 100ns or 80ns). Think about it; on a given SIMM there are EIGHT individual memory chips built from EIGHT individual pieces of silicon (they don't even have to be from the same manufacturer, but usually are) - those eight chips are certainly not matched down to the nearest nanosecond in their access times. In fact one could conceivably build a SIMM with a mixture of 80ns,100ns,120ns parts and call it a '120ns' SIMM. If TN176 says that SIMM speeds cannot be mixed then it is WRONG - as long as all the SIMMs meet or exceed (are faster) the required access time spec. I am intimately familiar with the various Mac memory interface circuits and have built numerous other DRAM controllers, and there is NO REASON why DRAM speeds cannot be mixed - as long as the required maximum access time is met. Remember, whenever you have more than ONE DRAM in a circuit you are mixing speeds! -- Don North ----- Apple Computer, Inc. ----- Advanced Technology Group UUCP: ...!{voder,nsc,decwrl,sun}!apple!north CSNET: north@Apple.COM {{ Facts are facts, but any opinions expressed are my own, and *do not* }} {{ represent any viewpoint, official or otherwise, of Apple Computer, Inc.}} + Organization: Apple Computer, Inc. -- Don North - via FidoNet node 1:105/14 UUCP: ...!{uunet!glacier, ..reed.bitnet}!busker!226!20!Don.North INTERNET: Don.North@f20.n226.z1.FIDONET.ORG
Amanda.Walker@f20.n226.z1.FIDONET.ORG (Amanda Walker) (12/28/90)
Reply-To: amanda@visix.com In article <47604@apple.Apple.COM> north@Apple.COM (Don North) writes: >Amanda is right; no if's and's or but's! > ... >I am intimately familiar with the various Mac memory interface circuits and >have built numerous other DRAM controllers, and there is NO REASON why DRAM >speeds cannot be mixed - as long as the required maximum access time is met. >Remember, whenever you have more than ONE DRAM in a circuit you are mixing >speeds! Whew. Thank you, Don. I was beginning to wonder if I'd switched universes some time when I wasn't looking. Grin. Now, if people start arguing with *you*, I may suggest starting a new newsgroup called comp.sys.mac.folklore :)... -- Amanda Walker amanda@visix.com Visix Software Inc. ...!uunet!visix!amanda -- "I used to be disgusted; now I'm just amused." --Elvis Costello + Organization: Visix Software Inc., Reston, VA -- Amanda Walker - via FidoNet node 1:105/14 UUCP: ...!{uunet!glacier, ..reed.bitnet}!busker!226!20!Amanda.Walker INTERNET: Amanda.Walker@f20.n226.z1.FIDONET.ORG