todd@ivucsb.sba.ca.us (Todd Day) (10/06/89)
Building a DSP board, Part Six: SM5805s, leave the driving to us
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This is the sixth in a series on how I went about building
a dual Motorola DSP56000 sampling board.
The SM5805 plays a major role in my board. It provides the signals
for driving the S/Hs, the DACs, the ADCs, and the 56000 itself.
We'll start on the input side of things and step thru all of the
signals that it generates.
Here's a diagram of the signals that apply...
Processor (clock) output:
---+ +-------
LRCK +---------------------------------------------------------------+
(left-right clock)
---+ +-------------------------------+
WDCK +-------------------------------+ +-------
(word clock)
SM5805 output:
---+ +---------------+
SH +-----------------------------------------------+ +-------
(sample/hold mode control)
+-+ +-+
CC ---+ +-------------------------------------------------------------+ +-----
(ADC convert command)
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +
BBC ----++-++-++-++-++-++-++-++-++-++-++-++-++-++-++-++-++--------------++-++-+
(bit rate clock)
ADC output:
DINL |ms|15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2|ls |ms|
(left channel data)
DINR |ms|15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2|ls |ms|
(right channel data)
+------------------------------------------------+ +-------
STATUS--+ +--------------+
(convert done)
Data to 56000:
+-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+
OBCK -+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-
(bit rate clock)
DOL |msb| 15| 14| 13| 12| 11| 10| 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 |lsb|msb| 15
(from SM5805 - merged bitstream) left channel at t-1 rt chan
After going thru the analog filters, the first thing that must be done
to the signal is sampling and holding. The reason the signal must be
held is that our ADC (like most 16bit ADCs today) uses successive approximation
to determine the analog value. It has a DAC inside. It tries a DAC value,
and if the analog signal is bigger, it increases the DAC value and tries the
comparison again. Remember that it is almost impossible to match the value
exactly, so it keeps retrying until it is within +/- 1/2 DAC step. If
the analog value wasn't held, the ADC might never converge.
Okay, look at the SH and CC signals. When SH is high, the sample/hold
lets the output signal float. When low, it clamps the analog value.
So, the SM5805 tells the s/h to hold the signal and then tells the ADCs to
sample the signal. BBC is the bit rate clock used to tell the ADCs to
get the next bit of serial data out the door. The first pulse on BBC
tells the ADC we are ready, and the next pulses clock out all 16 bits.
Note that these are not the 16 bits that go out the SM5805 in the merged
bitstream. The SM5805 uses the samples from t-1/2 (remember, the output
is decimated) and t-1 and t-n/2 all the way to n = 121 (it uses a 121st
order FIR filter) to generate the output at t.
The output is clocked by OBCK (this can be generated from the master
clock) for the bitrate, and LRCK and WDCK for the left/right channel
designation and the word clock. LRCK is the oversampling sample rate
and WDCK is twice that value.
The DAC side of things works almost completely the same way, except
that the merged bitstream is the input to the SM5805 and the oversampling
bitstream is the output. In other words, the SM5805 is interpolating.
Another small difference is that the oversampling bitstream completely
fills the time taken by the word clock, instead of just a portion.
The sample/holds hold the signal during the time that the output from the
DACs might have spikes.
BTW, I think I calculated that the highest (final, i.e. no oversampling)
sampling rate using my methods is about 52 kHz, so it will work with
DAT players.
Next: Serial Loader Bootstrap. Let's boot this puppy and run with it!
--
Todd Day | todd@ivucsb.sba.ca.us | ivucsb!todd@anise.acc.com
"Time to eat all your words, swallow your pride, open your eyes."
-- Tears for Fears