mrj@basser.oz (Mark James) (10/17/89)
Is it guaranteed that external memory accesses by the DSP56001 will be separated by a whole number of instruction cycles (i.e. 0,1,2..) when running with zero wait states or is it possible that the gap could be 1/2, 1 1/2, 2 1/2, ... cycles. Thank you. Mark James mrj@basser.cs.su.oz