zawada@EN.ECN.PURDUE.EDU (Paul J Zawada) (11/09/89)
murphy@pur-phy (William J. Murphy): > > I have thought of a way which might work. Keep a counter corresponding > to 0-15 which is incremented each time you D-A a bit. The counter would > be used as a multiplier for the voltage to be converted. So if the digital > signal was as follows, you would get the following voltages. > > BitValue VoltageCounter Voltage converted/output > 0 0 Vmin*(2^counter)*BitValue = 0 > 1 1 Vmin*2^1*1 = 2*Vmin > 1 2 Vmin*2^2*1 = 4*Vmin > 0 3 Vmin*2^3*0 = 0 > 1 4 Vmin*2^4*1 = 16*Vmin > Etc. ... > The only thing I wouldn't understand is where you "hold" the voltages you have converted. i.e. after you convert say, the first bit, you can't do anything with that voltage until you've converted the other 15 bits. Would there be some type of analog "memory" involved? The only other thing I could think of would to be to still have 16 D to A converters, but for some reason do the conversions individualy. Maybe it is designed to start the conversion process as soon as the first bit arrives and not wait for the other 15 bits....But why would you want to do that...it doesn't seem that it would speed up the conversion process all that much.. Anyone else have any ideas? pjz... Paul J Zawada | zawada@ee.ecn.purdue.edu "E-site" Student Consultant | ...!pur-ee!ei.ecn.purdue.edu!zawada Purdue University | Engineering Computer Network | GO BOILERS!!!
dean@image.soe.clarkson.edu (Dean Swan) (11/10/89)
From article <8911091355.AA20559@en.ecn.purdue.edu>, by zawada@EN.ECN.PURDUE.EDU (Paul J Zawada):
> all that much.. Anyone else have any ideas?
I don't know what they are in fact doing, but here are some thoughts on the
matter. First, If they in fact do anything close to what you are suggesting
, they are probably just using the comparator output of a kind of backwards
binary search DAC. I highly doubt it though.
What seems more reasonable is that they are using pulse width modulation
of a very high frequency carrier, and low pass filtering the output.
A good practical example of this technique can be found in the General
Instruments SP0256 speach synthesizer chip. The amplitude of the output
signal is directly proportional to the pulse width of the carrier.
-Dean Swan
dean@sun.soe.clarkson.edujharkins@sagpd1.UUCP (Jim Harkins) (11/11/89)
The guy who writes the technical column in CD Review discussed this in depth a month or two ago. I don't remember the details but evidently it's much better than the old-fashioned way. Sorry, my issue has long since gone to that great trash can in the sky. jim
aez@Data-IO.COM (Adam Zilinskas) (11/16/89)
I think what the real mechanism used in 1 or low bit DAC is that they digital data is oversampled, passed through a smaller simpler DAC and then low-pass filtered back to the desired shape. I have hiding somewhere a couple of references to some ICCAD papers on analog design where a company was using a 3-bit DAC, a cheapish low-pass filter and some DSP techniques on the oversampled signal to compensate for the low-pass. Here is a very simplistic 1 bit DAC example: digital bit -----|diode>-------+----+-------> "analog out" | | - - C R a e p s - - | | - - = = < -- "ground" To those that can't read my ASCII schematic, this is essentially a peak detector. The Low pass filter is an RC circuit. To generate "max" analog output, the digitial bit must always be one, "min" is when the digital bit is always zero. Now anything in between will have a the digital bit being one for a certain percentage of time (for 3/16*"max" output, a stream of 3 ones and 13 zeros should arrive at the each RC timeframe). The mechanism is very much like a switching power-supply (a controlled amount of charge is pumped out to maintain a desired voltage) except that the timeframe has to be particularly high to be useful. Note that if you breadboard this circuit up, the analog output would not be perfectly clean (due to the poor low-pass filter ;-). The technique makes the DAC cheap (almost non-existant) but puts the burden upon the low-pass filter (analog) or on the DSP technique (digital) to recover the information. Like a professor, I leave the mathematics as an exercize for the reader :-) problem 1. Find a reasonable RC constant for 100 Khz DAC. Problem 2. Determine the bit-period and frame size to generate a 50KHz sine wave with 16 bits accuracy. Extra Credit: Generate a Z-transform, DSP program... that will precompensate the 16 bit input to make this DAC work better. Adam Zilinskas "Gee this isn't a PLD, you shouldn't assume that Data I/O has anything to do with it or has responsibility for it. :-) "