cdc@uafhcx.uucp (C. D. Covington) (02/06/90)
In article <233@cmic.UUCP>, garvey@cmic.UUCP (Joe Garvey) writes: > 8 FIR filters, 16 taps, tap weights vary from filter to filter > Fixed pt arithmetic (final resolution ~ 6-8 bits), 1-D > 3-5 times over sampling of a 38.4KHz signal > Note: This means an aggregate rate of 3.072 MHz (MSamples) > Power and size are very important. ... > I've been looking at the A100 from Inmos. Its a variable resolution/length perhaps overkill What you are suggesting is a serious project, but my calculations indicate that you should be able to pull it off with something in the neighborhood of three DSP chips. TI's TMS32020 series chips or the DSP56000 stuff should approach the required processing power. A good DSP chip should be able to perform one tap per machine cycle, one cycle being 100ns or less. There is some overhead for setting up the loops, but something like the RPT repeat instruction makes this very fast. As far as power is concerned, CMOS is the best you can do I would think [e.g. TMS320C20 or TMS320C25]. C. David Covington INTERNET cdc@uafhcx.uark.edu Assistant Professor, Electrical Engineering (501)575-6583 campus office University of Arkansas 575-5379 research office Fayetteville, AR 72701 575-3041 research lab