distef@eecg.toronto.edu (Eugenia Distefano) (07/21/90)
The 96002's on-chip DMA controller can handle single-block or word-per-word transfers. If the former is chosen, is the external bus relinquished between words in case the cpu or an external device is requesting access to it? Is this dependent on the way the DMAP (DMA priority bit) is set? Thanks, -- Eugenia
johnf@oakhill.UUCP (John Fisher) (07/25/90)
> From: distef@eecg.toronto.edu (Eugenia Distefano) > Posted: Fri Jul 20 15:34:06 1990 > Organization: EECG, University of Toronto > > The 96002's on-chip DMA controller can handle single-block or word-per-word > transfers. If the former is chosen, is the external bus relinquished between > words in case the cpu or an external device is requesting access to it? Is > this dependent on the way the DMAP (DMA priority bit) is set? > > Thanks, > -- Eugenia Answer: You are correct, DMAP controls the priority between the 96002 CPU and the on-chip DMA controller as described on pages 7-48 and 49 of the User's Manual. Priority between the on-chip DMA controller and external bus masters such as an external CPU or DMA controller is determined by the external bus arbitration controller. This controller will monitor ~BR and generate BG~ each external bus cycle. Note that it is possible for ~BR to be continuously asserted by setting the RH bit in the BCR register (page 7-4). In this case the external bus arbitrator may dedicate the bus to the 96002 by contin- uously asserting ~BG in response to ~BR however this depends on the priority scheme implemented in the external bus controller.