mark@necntc.nec.com (Mark Medovich) (12/01/90)
>Subject: References wanted for Block-diagram compilers of Signal Flow Graphs >Keywords: DSP, question >Message-ID: <9011281311.AA04504@happy.ee.man.ac.uk> >Date: 28 Nov 90 13:11:26 GMT >Sender: compilers-sender@iecc.cambridge.ma.us >Reply-To: Andrew Nisbet (MSc) <andy@spec0.electrical-engineering.manchester.ac.uk> >Organization: Compilers Central >Lines: 24 >Approved: compilers@iecc.cambridge.ma.us >Xref: necntc comp.compilers:1561 comp.dsp:1055 >Hi, > I'm a research student doing some work on the simulation of DSP >algorithms which are specified as cyclic directed graphs (Signal Flow >Graphs). A node in such a graph represents an arbitrary function such as Hi, Are you familiar with the NEC uPD72181 Image Pipeline Processor(ImPP) (should have been called "Data Flow Processor")? If not, I would recommend contacting your local NEC representative and getting information. There are hundreds of pages of application notes and flow graphs, explanations, etc. Further, you'll be able to get your hands on hardware to execute the algorithms that you write. The ImPP is a very, very interesting device....a 40 pin device with 16 inputs, 16 outputs, several handshake and control lines, and power and ground. Up to 14 can be cascaded. Mark Medovich | mark@necntc.nec.com | ..harvard!necntc!mark A secret report from within the Guild... It is by will alone I set my mind in motion.