shif@aplpy.jhuapl.edu (Gary D. Shiflett) (05/28/91)
I am working on a project to determine the feasibility of developing an ultra-high speed FFT digital signal processor. The notional requirements for the A/D converter subsystem are 360 million complex samples per second (or 720 real MSPS) at 7 effective bits. My questions are: 1) What is considered state-of-the-art in ADCs? 2) Who are the players? 3) Which is the preferred sampling architecture, e.g., direct, analog or digital quadrature, analog or digital Hilbert, at these rates and why (general)? 4) Does anyone know of any POCs for ADC work in the Advanced Circuits Technology Group at Hughes (El Segundo)? Thanks in advance, -- Gary Shiflett Applied Physics Laboratory Johns Hopkins University shif@aplpy.jhuapl.edu