hdrw@ibmpcug.co.uk (Howard Winter) (06/26/91)
[about whether DRAM chips with a faster speed rating than needed should work] You are right, he is wrong - the speed rating is related to the time the chip needs for its output data to stabilise after the 'Read' signal is asserted (for the purists - this is s Gross Simplification). Having chips that are too fast just means they sit around with valid data for longer - They should work perfectly. The only other parameter which could affect things is how often they need to be refreshed, and I can't imagine that's going to be a problem - the refresh allowance is normally very generous - otherwise unreliable memory would result. Also this doesn't sound like your problem. Power requirement normally goes up with faster chips, but unless the PSU is almost at its limit in the original setup, that's unlikely to be it either. BUT there are two modes of accessing SIMMs - and this is where I can't remember the details, but I think its page mode and interleave mode. Not all DRAMs can do both, I think, so it could be yours are being driven by the Dell in a mode they aren't designed to use. Someone else can probably fill in the details of this - sorry I can't do so. Good luck Howard. -- Automatic Disclaimer: The views expressed above are those of the author alone and may not represent the views of the IBM PC User Group. -- hdrw@ibmpcug.Co.UK Howard Winter 0W21' 51N43'
dwgordon@matt.ksu.ksu.edu (Dwight W. Gordon) (06/26/91)
hdrw@ibmpcug.co.uk (Howard Winter) writes: >[about whether DRAM chips with a faster speed rating than needed should work] >You are right, he is wrong - the speed rating is related to the time the chip >needs for its output data to stabilise after the 'Read' signal is asserted >(for the purists - this is s Gross Simplification). Having chips >that are too fast just means they sit around with valid data for >longer - They should work perfectly. >-Howard. Not exactly correct. There is a possibility that the data may become valid too soon. I teach my students about microprocessor timing in my courses. One of the problems that can occur is data latency from a previous device access. Old data from some other device may be on the bus at the same time that the RAM data appears. This causes a bus conflict. This may manifest itself in the form of a parity error. (I used to consult for a company that repaired IBM desktops. Original IBM-PC/XTs used a combinational logic design to detect parity. Results were sent to the NMI*. Bus conflicts caused parity errors - sometimes.) With a reasonable design this problem is unlikely unless you go overboard (<80nS parts in a board designed for 120nS). These numbers are just examples. Without a complete timing analysis of the system (which, I suspect, not even some manufacturers are doing), there is no guarantee. - Dwight - -- Dwight W. Gordon, Ph.D. Kansas State University dwgordon@matt.ksu.ksu.edu Electrical and Computer Engineering dwgordon@ksuvm.bitnet Durland Hall Phone 913-532-5600; FAX 913-532-7810 Manhattan, KS 66506-5105