jmk@alice.UUCP (08/16/89)
The M/120 RISComputer Technical Reference of July 1988 states on page 3-7 Level 5 interrupt (Intr5*)... This interrupt is reset when the interrupt handler reads the contents of the Fault Address Register, ... Whereas, on page 3-11 we find The captured fault address is held until software reads the Interrupt Status Register (ISR). Reading the ISR causes the Intr5* signal to be de-asserted... Which is correct? Jim McKie research!jmk -or- jmk@research.att.com Bell Laboratories