byrd@portia.Stanford.EDU (Greg Byrd) (10/03/89)
This may be a naive question, but... In Kane's MIPS R2000 book, I can't find any reference to atomic instructions, like swap or test-and-set. Are there really none, or am I missing something? If not, how do MIPS-based multiprocessors implement locks?
jeffd@norge.sgi.com (Jeff Doughty) (10/03/89)
> This may be a naive question, but... > In Kane's MIPS R2000 book, I can't find any reference to > atomic instructions, like swap or test-and-set. Are there > really none, or am I missing something? If not, how do > MIPS-based multiprocessors implement locks? It is not naive at all. The SGI PowerSeries machines, which use multiple R2000's and R3000's implement test-and-set spinlocks with a custom gate-array per processor and a private bus. The gate-array is actually a bus-watching cache that maintains the state of 64K spinlocks. We kernel guys grab 32K and allow the users 32K. They are mapped into a process's address space and accessed like memory. Moving the synchronization traffic to a separate bus has several advantages - the primary reason being that it takes load off the memory bus. In addition, we can taylor the latency requirements and cache coherency protocols to lock traffic, rather than having one bus design that does everything non-optimally). Jeff Doughty IRIX group Silicon Graphics, Inc.