[comp.sys.mips] Gary Kane++

anderson@granite.cr.bull.com (David Anderson) (12/21/89)

     Just wondering...

     It seems that MIPS has thrown out "upward compatibility" in designing 
     the 6000, since "/usr/include/sys/immu_r6000.h" defines 16K pages,
     a resulting difference in the TLB EntryLo register, i.e. a 22 bit PFN, 
     and of course a change in all of the page-size-related constants.

     Is there an addendum or update to Gary Kane's book that outlines
     the differences between MIPS current processor line and the upcoming
     6000?  

==============================================================================
     Dave Anderson                     
     Bull HN Information Systems       anderson@granite.cr.bull.com
     300 Concord Road.
     Billerica, MA 01862               508-671-3253
==============================================================================

rogerk@mips.COM (Roger B.A. Klorese) (12/22/89)

In article <1989Dec21.150346.10211@granite.cr.bull.com> anderson@granite.cr.bull.com (David Anderson) writes:
>     It seems that MIPS has thrown out "upward compatibility" in designing 
>     the 6000, since "/usr/include/sys/immu_r6000.h" defines 16K pages,
>     a resulting difference in the TLB EntryLo register, i.e. a 22 bit PFN, 
>     and of course a change in all of the page-size-related constants.

Upward compatibility for user-mode programs is guaranteed.  Kernel-mode
and diagnostic-mode software is indeed incompatible, but some of it is
incompatible between machines implemented with R2000s or R3000s (due to
different memory system implementations, etc.).

>     Is there an addendum or update to Gary Kane's book that outlines
>     the differences between MIPS current processor line and the upcoming
>     6000?  

Remember that the RC6280 is not yet shipping, and the R6000 chipset is
not announced as a chip product.

There is a new edition of the Book "MIPS RISC Architecture" (by Joe Heinrich
and Gerry Kane) currently in review, for publication early next year.  It
covers the ISA extensions, as well as more detail, opcode bit patterns,
etc. for all MIPS processors.
-- 
ROGER B.A. KLORESE      MIPS Computer Systems, Inc.      phone: +1 408 720-2939
928 E. Arques Ave.  Sunnyvale, CA  94086                        rogerk@mips.COM
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