[comp.sys.mips] slattach "load", e.t.a. for 4.50B

lamy@mailrus.uucp (Jean-Francois Lamy) (07/24/90)

Running slattach on tty1 on a RC3230 results in it showing up by "top" as
gobbling up 90-92% of the CPU when the machine is idle, and piling up
execution time.  I am almost certain the load figure is artificial (90% of 18
MIPS is a whole loot of cycles :-) and likely due to the way slattach is
coded, but would like an explanation nonetheless (heck, if I wasn't curious I
wouldn't be in this business :-)

Also, what is the estimated time of arrival for the modem control fixes for
the tty ports on 3230s?  Also, can anyone provide more details concerning the
nature of the "IC availability problems" or "Does not work with serial board
sold by MIPS" explanations I've heard about the ISA slot adapter failure to
ship?

Jean-Francois Lamy               lamy@sobeco.com, uunet!sobeco!lamy
Groupe Sobeco, 505 ouest, bd Rene-Levesque, Montreal Canada H2Z 1Y7

brudley@mips.COM (Brett Rudley) (07/25/90)

In article <9007240032.AA02339@sobeco.sobeco.com> uunet!sobeco.sobeco.com!lamy@mailrus.uucp (Jean-Francois Lamy) writes:
>Running slattach on tty1 on a RC3230 results in it showing up by "top" as
>gobbling up 90-92% of the CPU when the machine is idle, and piling up
>execution time.  I am almost certain the load figure is artificial (90% of 18
>MIPS is a whole loot of cycles :-) and likely due to the way slattach is
>coded, but would like an explanation nonetheless (heck, if I wasn't curious I
>wouldn't be in this business :-)

>
>Also, what is the estimated time of arrival for the modem control fixes for
>the tty ports on 3230s?  Also, can anyone provide more details concerning the
>nature of the "IC availability problems" or "Does not work with serial board
>sold by MIPS" explanations I've heard about the ISA slot adapter failure to
>ship?

I believe 4.50B is shipping already.  This includes a fix for the modem
controls on the tty ports as well as getting the AT bus based serial IO
card to function properly.  The bus adapter was changed to use edge triggered
interrupts rather than level interrupts fairly late in the development
cycle and the changes to the driver did not make it into 4.50.  4.50B includes 
these changes.

>

>Jean-Francois Lamy               lamy@sobeco.com, uunet!sobeco!lamy
>Groupe Sobeco, 505 ouest, bd Rene-Levesque, Montreal Canada H2Z 1Y7


-- 
Brett Rudley 		       {ames,decwrl,pyramid,prls}!mips!brudley
MIPS Computer Systems	           - or -
930 Arques Avenue 	       brudley@mips.com
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