tbaldonid@cc.curtin.edu.au (Danny Baldoni) (09/28/90)
Can anybody tell me where I can find details on the instruction set and the binary formats for the instructions on an R2000/R3000 (and associated R2010/R3010) processor? If you're unfortunate enough to have to do some assembly-level optimising, relying on just an assembler manual really isn't much help. I'd prefer if people mail replies to me and I'd be happy to summarise those replies for the Net. Thanks folks for any help you can provide. ------------------------------------------------------+------------------------ Phone: +61-9-351-7450 | Daniel Baldoni PSImail: psi%050529452300070::TBALDONID | Computing Science Internet: TBALDONID@cc.curtin.edu.au | Curtin University ACSnet: TBALDONID@cc.cut.oz.au | GPO Box U1987 Bitnet: TBALDONID%cc.curtin.edu.au@cunyvm.bitnet | Perth UUCP: uunet!munnari.oz!cc.curtin.edu.au!TBALDONID | Western Australia, 6001 ------------------------------------------------------+------------------------ "Any time there's something so ridiculously dangerous that no rational human being would even consider trying it, they send for me" - Belgarion, "King of the Murgos" by David Eddings -------------------------------------------------------------------------------
cprice@mips.COM (Charlie Price) (09/29/90)
In article <3774.27031c0e@cc.curtin.edu.au> tbaldonid@cc.curtin.edu.au (Danny Baldoni) writes: > >Can anybody tell me where I can find details on the instruction set and >the binary formats for the instructions on an R2000/R3000 (and associated >R2010/R3010) processor? This gets asked a lot, so a posting (rather than just email) seems in order. There is a book by Gerry Kane that is a description of the MIPS architecture and the implementations in the R2000/R3000 (CPUs) and R2010/R3010 (FPUs). The R2000/2010 and R3000/3010 are essentially identical at the instruction level The book includes tables of instruction encodings. The first edition was published before the R3000/R3010 were done and the choice of title was unfortunate in view of the R2000-R3000 similarity. It was titled: MIPS R2000 RISC Architecture The second (and current) edition is titled: MIPS RISC Architecture Both editions are by Gerry Kane and published by Prentice Hall. the reference numbers are: 0-13-584749-4 ISBN 88-060290 Library of Congress Card Number This will not be the final word. I am currently reviewing an alpha draft of the next edition also titled "MIPS RISC Architecture". This edition will cover both the MIPS I architecture (the R2000/2010/3000/3010) and the extensions in the MIPS II architecture (the R6000 and R6010). -- Charlie Price cprice@mips.mips.com (408) 720-1700 MIPS Computer Systems / 928 Arques Ave. / Sunnyvale, CA 94086-23650
grunwald@foobar.colorado.edu (Dirk Grunwald) (09/29/90)
how timely. What's the difference between the R2000 and R3000 at an architectural level. A local person debating between DEC and IBM machines found that the DS5000 (with an r3000) gives ~15MF on addition, which he found hard to believe. Taking a linear scaling from a DS3100 (R2000 based), I'd agree, since the DS5000 seems to be 75% to 100% faster than the R2000, from which I can pull about 3MF, downhill with a tailwind.
craig@netcom.UUCP (Craig Hansen) (09/29/90)
There is no difference between the R2000/R2010 and the R3000/R3010 in instruction set and latency of operations (in cycles). The peak execution rate of floating-point adds in either chip set is 1/2 of the processor clock rate: a floating-point add has 2 cycles of latency. In fact, if you are very careful, you can intermix single-precision floating-point multiplies and adds and maintain that same rate: 2 FP ops in 4 cycles. 15 MFLOPS is achieveable for a 30 MHz machine. The chips only differ in their pin-out, maximum cache size, and memory interface features. Perhaps you were talking about a benchmark that took cache misses... Regards, Craig Hansen craig@microunity.com
grunwald@foobar.colorado.edu (Dirk Grunwald) (10/02/90)
>>>>> On 29 Sep 90 02:01:45 GMT, craig@netcom.UUCP (Craig Hansen) said:
CH> There is no difference between the R2000/R2010 and the R3000/R3010
CH> in instruction set and latency of operations (in cycles).
---
what *does* differ between the r2000/r3000? TLB size? write buffer depth?mark@mips.COM (Mark G. Johnson) (10/02/90)
In article <27355@boulder.Colorado.EDU> grunwald@foobar.colorado.edu writes: > >what *does* differ between the r2000/r3000? TLB size? write buffer depth? > A subset of the differences [doing this from home :-( so there are more...] (1) clock rate: if r3000 then MHz > 16.7 (2) Block Refill: upon Icache miss, transfer ni (>=1) words from main memory to Icache in a block ... "block refill". Upon Dcache miss transfer nd words between Dcache and main memory. ni and nd independently settable at bootstrap time. R3000 has this, R2000 does not. (3) Streaming: When a block refill is occuring, don't stall the machine waiting until the last word in the block is transfered. As soon as the word arrives that you wanted, restart the machine. As the remaining words in the block whizz by, on their way to the cache, tap them as needed into the CPU (avoids installing a 2nd port on the caches). R3000 only. (4) Internal electrical details that support higher clock rates for r3k such as larger number of VDD/GND bondpads and bondwires, additional on-chip metallization, etc. -- -- Mark Johnson MIPS Computer Systems, 930 E. Arques M/S 2-02, Sunnyvale, CA 94086 (408) 524-8308 mark@mips.com {or ...!decwrl!mips!mark}