appel@cs.Princeton.EDU (Andrew Appel) (12/08/90)
If a process (like an interactive programming language environment, or a compiled-code circuit simulator, etc.) wants to generate machine code, put it in the data space, and then execute it, it's necessary to flush the I-cache (for the appropriate address region) using "cacheflush" for proper execution.
mash@mips.COM (John Mashey) (12/15/90)
In article <5159@rossignol.Princeton.EDU> appel@cs.Princeton.EDU (Andrew Appel) writes: >If a process (like an interactive programming language environment, >or a compiled-code circuit simulator, etc.) wants to generate machine >code, put it in the data space, and then execute it, it's necessary >to flush the I-cache (for the appropriate address region) using "cacheflush" >for proper execution. This (cacheflush, or equivalent) is needed on ony machine that uses: a) Separate I & D caches, that b) Are not synchronized by hardware There are good technical reasons for building such machines. In particular, they include, at least: IBM RS/6000 Intel i860 MIPS R3000 & R6000-based machines Motorola 68040 Motorola 88K (in normal use; most OS's turn off I-coherency for performance reasons) and (I think) HP PA, Clipper And although current SPARCs have a joint I&D cache, they also define an instruction for flushing the I-cache, to allow for possible designs with split caches. Of course, everyone's programmatic interface is different to cause the flush.. -- -john mashey DISCLAIMER: <generic disclaimer, I speak for me only, etc> UUCP: mash@mips.com OR {ames,decwrl,prls,pyramid}!mips!mash DDD: 408-524-7015, 524-8253 or (main number) 408-720-1700 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086