jhh@sprite.Berkeley.EDU (John H. Hartman) (02/08/91)
I'm having a strange problem on the ds5000/200 that has to do with the cache and partial writes. I have a user-level process that is sharing a piece of memory with the kernel. The kernel accesses the memory through kseg0 (unmapped and cached), while the user accesses it through kuseg (mapped and cached). The kernel is writing 2-byte items, and the user process is reading them. When the kernel first writes to a particular cache line it is not in the cache. Things work fine if there is only one item in a cache line. The kernel writes the item, which bypasses the cache and is written to memory. The user process then reads the item, causing the line to be read into the cache. If there is more than one item on a line then things break. Everything works ok for the first item, but when the user process reads the second item it does not read the value that the kernel just wrote. Instead it gets the value when the first item was read, ie the value when the cache line was first brought into the cache. Here is the sequence of events: Item1 and Item2 are both 0, on the same cache line, and not in the cache. Kernel stores 1 into item1. User reads 1 from item1. (cache line brought into cache) Kernel writes 1 to item2. (should be written to cache) User reads 0 from item2. (should have read 1) It appears to me that the kernel write of item2 is bypassing the cache, since the user process will see the correct value if the cache line is flushed from the cache before it reads it. Also, the user process will see the correct value if the kernel reads item2 before or after writing it. Can someone tell me what is contained in the cache tags for this machine? I don't see how having the kernel read item2 before the user process solves the problem. Has anyone had a similar experience? John ----------------------------------------------------------------------- John H. Hartman Graduate Student, UCB Sprite project jhh@sprite.berkeley.edu