jdp@polstra.UUCP (John Polstra) (04/25/91)
I have a couple of arcane questions about the integer pipeline on the MIPS R2000 and R3000. 1. In the following sequence of instructions, is register $4 guaranteed to end up with the value contained in memory location "bbb"? lw $4, aaa lw $4, bbb 2. In the following sequence of instructions, is register $4, guaranteed to end up containing zero (regardless of what is contained in memory location "aaa")? lw $4, aaa move $4, $0 I notice in each case that the MIPS assembler does not insert a NOP after the first load instruction. Note: these examples will seem less stupid if you imagine that the first instruction is in the delay slot of a conditional branch. Thanks -- enquiring minds want to know . . . -- John Polstra polstra!jdp@uunet.uu.net Polstra & Co., Inc. ...!uunet!polstra!jdp Seattle, Washington USA (206) 932-6482 "Self-knowledge is always bad news." -- John Barth
keith@MIPS.com (Keith Garrett) (05/01/91)
In article <8179@polstra.UUCP> jdp@polstra.UUCP (John Polstra) writes: >I have a couple of arcane questions about the integer pipeline on the >MIPS R2000 and R3000. > >1. In the following sequence of instructions, is register $4 guaranteed >to end up with the value contained in memory location "bbb"? > > lw $4, aaa > lw $4, bbb yes > >2. In the following sequence of instructions, is register $4, guaranteed >to end up containing zero (regardless of what is contained in memory >location "aaa")? > > lw $4, aaa > move $4, $0 yes > >I notice in each case that the MIPS assembler does not insert a NOP >after the first load instruction. Note: these examples will seem less >stupid if you imagine that the first instruction is in the delay slot of >a conditional branch. the load delay only affects the availability of the data for the following instruction. the writes to the register file occur in order. lw $4, aaa IF RD ALU MEM WB lw $4, bbb IF RD ALU MEM WB move $4, $3 IF RD ALU MEM WB ^ ^ ^ ^ ^ ^ ^ | | | | | | | |address required for 1st load | | |data from 1st load available | | | |data from 1st load in register | |address required for 2nd load | | | | |data from 2nd load available | | | | | |data from 2nd load in register | | |data required for 3rd op | | | | |data from 3rd op available | | | | | | |data from 3rd op in register > >Thanks -- enquiring minds want to know . . . you're welcome. i hope this helps -- Keith Garrett "This is *MY* opinion, OBVIOUSLY" (408) 524-8110 Mips Computer Systems, 930 Arques Ave MS 1-02, Sunnyvale, Ca. 94088-3650 "Beware of the half-truth - you may have gotten hold of the wrong half." keith@mips.com -or- {ames,decwrl,prls}!mips!keith -Rabbi Seymour Essrog
ychen@sp1.csrd.uiuc.edu (Yung-Chin Chen) (05/03/91)
In article <8179@polstra.UUCP> jdp@polstra.UUCP (John Polstra) writes: > I notice in each case that the MIPS assembler does not insert a NOP > after the first load instruction. Note: these examples will seem less > stupid if you imagine that the first instruction is in the delay slot of > a conditional branch. Don't reply on assembly code (compile with -S option). That is not the real object code. The smart MIPS assembler will re-ordering these codes to eliminate register interlock problems. Your question is only one case of such problems. Only re-ordering failure ( instruction shuffle will result in incorrect execution) will result an extra NOP instruction. That is what I know and I hope it is right. ychen ---------------- UIUC, CSRD
bruce@cs.su.oz (Bruce Janson) (05/03/91)
In article <YCHEN.91May2180007@sp1.csrd.uiuc.edu> ychen@sp1.csrd.uiuc.edu (Yung-Chin Chen) writes: >.. > Don't reply on assembly code (compile with -S option). That is not >the real object code. The smart MIPS assembler will re-ordering these >.. Yes, /usr/bin/dis will display the real machine instructions. See dis(1-SysV) for details. Cheers, bruce. Bruce Janson Email: bruce@cs.su.oz.au Basser Department of Computer Science Phone: +61-2-692-3272 University of Sydney, N.S.W., 2006, AUSTRALIA Fax: +61-2-692-3838
jdp@polstra.UUCP (John Polstra) (05/07/91)
In article <YCHEN.91May2180007@sp1.csrd.uiuc.edu> ychen@sp1.csrd.uiuc.edu (Yung-Chin Chen) writes: >In article <8179@polstra.UUCP> jdp@polstra.UUCP (John Polstra) writes: > >> I notice in each case that the MIPS assembler does not insert a NOP >> after the first load instruction. Note: these examples will seem less >> stupid if you imagine that the first instruction is in the delay slot of >> a conditional branch. > > Don't reply on assembly code (compile with -S option). That is not >the real object code. The smart MIPS assembler will re-ordering these >codes to eliminate register interlock problems. Your question is only >one case of such problems. Only re-ordering failure ( instruction >shuffle will result in incorrect execution) will result an extra NOP >instruction. That is what I know and I hope it is right. > >ychen >---------------- >UIUC, CSRD Yes, I was aware that the MIPS assembler reorders instructions. I did examine the actual object code, using DBX. Keith Garrett of MIPS answered my questions with a very informative post. Briefly, when two consecutive instructions both modify the same register, the second instruction will always determine the final content of the register. -- John Polstra polstra!jdp@uunet.uu.net Polstra & Co., Inc. ...!uunet!polstra!jdp Seattle, Washington USA (206) 932-6482 "Self-knowledge is always bad news." -- John Barth