[comp.unix.i386] RAM speeds summary

greg%pipe@gatech.edu (Greg Williams) (04/11/89)

Here's the summary of responses from the question about RAM speeds
on 386 machines.

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 What is the truth about RAM speeds and true zero wait state 386 machines?
 I've seen ads that claim a 16MHz 386 must have 80ns RAM to achieve true
 zero wait state, but I've also seen people trying to sell 20 and 25MHz 
 machines with 80ns and some times even 100ns. Some of these machines are
 very cheap clones which do not seem to have special cache circuitry.
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From: John Lilley <lilley@boulder.Colorado.EDU>

As far as I know, the following is true:

For no cache, no interleave, no static column, zero-wait state:
16Mhz = 80ns
20Mhz = 60ns

I don't think there are DRAMS faster than that, altough there are
(very expensive) SRAMS.

With interleaving, I think that 20Mhz requires only 100ns.
However, that gets you about 1/2 wait state, not 0; because it
works only if you keep accessing sequential 32-bit words.  Accessing the
same interleaved bank twice in a row requires 1 wait state.  Of course,
interleaving means that you always need to buy two banks at a time.
In other words, for 256k DRAMs you buy in increments of 2MB.
For 1MB DRAMS, 8MB incrments.

Static column DRAMs (used by Compaq and Micronix), cache one "column"
internally in each chip, meaning that if you keep accessing  the same "column",
you get 1 wait state the first time, and zero thereafter.  One column
is (this can vary) 512 DWORDS (2k) for 256k chips, and 1k DWORDS (4k) for
1MB chips.  This also yields about 1/2 wait state.  Be careful of how
static column DRAMS are rated, however; some manaufacturers specify the
static column access time and others specify the non-static time.

Hope this helps.
--john lilley


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From: ward%cfa@harvard.harvard.edu (Steve Ward)

I just got some promotional literature direct from Intel which says
that the new 386SX at 16MHZ will run 0 wait state with 100ns DRAM's.
The literature makes a big deal of the special (different from standard
386) pipelining that allows use of such "slow" DRAM at 0 wait, as
compared to the standard 386, though there is no reference to the needed
DRAM speed for 0 wait state standard 386 operation at 16MHZ.  Still,
from this literature I would guess that a standard 386 at 16MHz would
need at LEAST 80ns DRAM.  The assumption here is that no cache is
used, of course.

steve w.   ward@cfa.harvard.edu

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From: karl@ddsw1.mcs.com (Karl Denninger)

Without interleaving, you are right.  

The clones get their 0 wait states by interleaving alternate RAM accesses,
such that one bank of memory is precharging while the other is being
accessed.  Done cleverly, it is possible to get 0 wait state operation from
100ns RAMs in a 20Mhz machine.

'Fer instance, the machines we sell are 20 Mhz, and use 100ns DRAMS.  The
limitation is that you must (if using 1MB DRAMs) expand in 4MB increments so
that the interleave works.  Thus, with 1MB DRAMS, you can have 4MB, 8MB,
12MB or 16MB -- with 256K's you can have 1, 2, 3 or 4MB.  It is forbidden to
mix chip types within the paired banks (ie: banks 1 & 2 must be both either
256K or 1MB DRAMs, same with banks 3 & 4).

My only complaint is that it is a real BITCH to discover which chip is bad
when you have a RAM failure, as the addresses don't correspond (necessarially)
with chip position anymore!

--
Karl Denninger (karl@ddsw1.MCS.COM, <well-connected>!ddsw1!karl)
Public Access Data Line: [+1 312 566-8911], Voice: [+1 312 566-8910]
Macro Computer Solutions, Inc.

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From: james@bigtex.cactus.org (James Van Artsdalen)

You can't get true zero-wait-state 386s.  Dell (my employer) made the
only one for a while, but we no longer sell it.  You can't get zero
wait state without an all-static design.
-- 
James R. Van Artsdalen          james@bigtex.cactus.org   "Live Free or Die"
DCC Corporation     9505 Arboretum Blvd Austin TX 78759         512-338-8789




greg%pipe@gatech.edu
GREG WILLIAMS "Barbaric Penguin"
Disclaimer: The usual stuff.