[ut.ee] IRAM :cider Friday 24th - Duncan Elliott

dunc@eecg.toronto.edu (Duncan Elliott) (11/22/89)

                Electrical Engineering Computer Group
                         Cider Seminar Series

        IRAM: Memory with a SIMD Processor Which Packs a Punch

                           Duncan Elliott &
                           Martin Snelgrove
                Electrical Engineering Computer Group
                        University of Toronto

         Time: Friday, Nov. 24, 1989, 12:05 --- Place: GB 248

       The architecture which we call IRAM is a hybrid of a RAM and  a
  SIMD  (single  instruction  path  multiple  data path) processor.  A
  single bit processor element (PE)  is  placed  next  to  each  sense
  amplifier within the RAM chips.  The PEs are cheap to integrate into
  the memory, exploit the tremendous memory bandwidth internal to  the
  chip  and,  if  used as computer main memory, can communicate with a
  more conventional processor via ``shared memory''.

       Using state of the art RAM technology, a  desk-top  workstation
  equipped  with  32MB  of IRAM might handle 58 billion 32-bit integer
  operations (analogous to 58000 MIPS) or 1.2 GFLOPS (double precision
  IEEE  floating  point  multiplications)  peak.   To  date, a smaller
  proof-of-concept  IRAM  has  been   designed   and   submitted   for

       This talk will focus on the IRAM architecture and how  to  keep
  it  busy.   A prize will be offered to the person who can dream up a
  better name for IRAM.

                             Coming Soon

 Date          Who                               Topic

Dec. 1    Mike Jenkins     Everything you always wanted to
                           know about research funding
Jan. 19   Pierre Delisle   A Load Balancing Facility for Distributed Systems