clawin@gypsy.ims.fhg.de (Detlef Clawin) (07/19/90)
In "Logic Minimization Algorithms for VLSI Synthesis", by R. Brayton ....
dealing with "espresso" several Berkeley PLA benchmarks are referenced,
e.g. ADD6, ADR4, ALU1. They are commonly referenced by other authors
for benchmarking logic optimization tools.
Does anybody know about a source for this benchmarks ore other
commonly used benchmarks ?
Any hints and remarks will be appreciated .
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