buchs@MAYO.EDU (Kevin J. Buchs) (02/07/90)
Archive-name: cosmos/24-Jan-90 Original-posting-by: buchs@MAYO.EDU (Kevin J. Buchs) Original-subject: Summary of responses to "Fault Simulation" Archive-site: vlsi.cs.cmu.edu [128.2.254.129] Archive-directory: /usr/cosmos/ftp Reposted-by: emv@math.lsa.umich.edu (Edward Vielmetti) This is a summary of responses to my recent posting inquiring about Fault Simulators. Several respondents informed me that there are no fault simulation tools with the Berkeley Magic set. The Berkeley toolset is not available via FTP. Write to this address for information on getting the toolset on a tape. Software Distribution Office Dept. of EE and CS Electronics Research Laboratory 479 Cory Hall University of California at Berkeley Berkeley, CA 94720 Bob Mayo (mayo@decwrl.dec.com) suggested a similar address with the first three lines above replaced by: Industrial Liaison Office. Bob gave a phone number of (415) 643-6687. There is another source for the Magic tools as suggested by Don (bouldin@sun1.engr.utk.edu). The Northwest Laboratory for Integrated Systems has a new release, version 3.2, of its VLSI design software that contains tools written at the University of Washington as well as U.C. Berkeley, CMU and MIT. MOSIS scalable CMOS is fully supported. This release is available to United States and Canadian universities only for a one-time handling/distribution fee of $200. Features of Release 3.2 are: Network C is a multilevel simulation system that allows modeling of functional units, gates, MOS transistors and arbitrary analog devices. (Bill Beckett, UWash) Gemini compares device netlists for isomorphism. (Carl Ebeling, UW) WIN is a specialized circuit design language for assembling layouts and netlists. (Wayne Winder and Rudolf Notrott, UWash) Ohmics checks CMOS designs to determine if ohmic contacts have been placed sufficiently close to transistors. (Wayne Winder, UWash) CFL is a library of routines that allows parametrized layouts to be assembled within C programs. (Bill Beckett, UWash) Magic, the graphical layout editor, and the entire 1986 UCB distribution. (Ousterhout et al, UCB) X version 11 drivers for Magic. (Warren Jessop, UWash) Rnl, the linear level timing simulator. (Chris Terman, MIT) Layout generators for a variety of circuits, including instantiated pad- frames, a dual ported RAM, a ROM and a variety of decoders. Supported platforms include IBM RT, SUN 3, and DEC VAX. All inquiries should be addressed to: Vicky Palm or Tony Marriott NW Lab for Integrated Systems Dept. of Comp. Science, FR-35 University of Washington Seattle, WA 98195 (206)-545-3796 palm@cs.washington.edu Allan Anderson (anderson@vlsi.ll.mit.edu) suggested the COSMOS simulator from Carnegie Mellon which is avaliable via FTP using the following data: machine: vlsi.cs.cmu.edu login: anonymous password: guest go to /usr/cosmos/ftp I was able to successfully obtain a copy of COSMOS this way. Another respondent suggested first contacting Randy Bryant at bryant@vlsi.cs.cmu.edu for information about COSMOS More than COSMOS is available from CMU. Don Bouldin provided this information. The SRC-CMU Research Center for Computer-Aided Design has developed and distributes a number of CAD tools. These tools consist primarily of systems of interrelated programs rather than isolated packages. The utility routines are shared among many programs. The standard tape currently includes: COSMOS, a compiled switch-level MOS simulator; the Process Engineer's Workbench (PEW), a system for statistical process and circuit design and simulation, including the FABRICS II simulator; the System Architect's Workbench (SAW), a behavior to structure synthesis system; the MX graphical user interface toolkit; and a variety of utilities including a GKS library, CIF plotter, and abstract data type library. The tape also includes the following software that is no longer in use, and is distributed as a source of ideas only: the CINNAMON 1.1 event- driven timing simulator; the Compost GKS-based drawing program; the ISPS simulation system; and the MASON min-cut floorplanner. The CAD Center distributes software on an as-is, internal-use only basis, as specified by the software release form which must be completed prior to software distribution. The handling charge is currently $100. The software is known to run on VAXs running 4.3bsd UNIX and DECstations running ULTRIX 3.1. Some software requires X11 Release 3 or DECwindows. Some of the software has been tested on Apollo and Sun workstations. GKS graphics support is available for a variety of workstations, terminals, plotters, and printers. The tape media is a 0.5" reel written in 6250BPI UNIX tar format. The tape contents is currently about 40 megabytes. The binary files for SAW, PEW, and COSMOS require about 15 megabytes. To order, contact: SRC-CMU Research Center for Computer-Aided Design Carnegie Mellon University Department of Electrical and Computer Engineering Pittsburgh, PA 15213-3890 Phone: (412) 268-8889 Internet: hank.walker@ece.cmu.edu Dave Smith (drs@sbcs.sunysb.edu) from SUNY, Stony Brook reported that he had been using the SLS simulator from the technical Univ of Delft, Netherlands. This is a very good simulator with three modes for: (1) pure logic simulation based only on the netlist and transistor types (2) logic simuloation based on actual circuit parameters (trans dimensions and interconnect R C) (3) timing version which also computes delays. To run it from Magic the staff at SUNY-SB wrote an ext2sls routine. You can get this from Dave. For Delft tools contact: rene@dutentb.tudelft.nl You may also contact Dave Smith at Dept CS, SUNY, Stony Brook, NY, 11794. William H. Nicholls (nicholls@atc.boeing.com) suggested the CHIEFS simulator from the University of Illinois. Does anyone have further information or an address for information about CHIEFS? William said he thinks a simple fault simulator comes with the majhong test generator with the Berkeley tools. More than one respondent asked for further information about HITS. My knowledge about it is sketchy at this point. HITS is an acronym for Hierarchical Integrated Test Simulator. It is a fault simulator with a large library of TTL parts. User models may also be created in a FORTRAN variant. The resultant model is compiled in FORTRAN. It is supported (actively) by: Avionics Support Equipment Division Support Equipment Engineering Department Naval Air Engineering Center Lakehurst, NJ 08733 To the best of my knowledge, we do not pay any fee for it. I only know for sure that it is available on VAX/VMS since that is what we use. I would not be surprised if that is the only host/OS. It seems to be most popular for use as a field fault diagnosis tool. There is about a foot worth of documentation available, although I do not know of any papers written about HITS. Jen-I (pi@vlsi-cad.isi.edu) asked for more information about MagiCAD. MagiCAD is a complete Computer Aided Design (CAD) system, operating in a VAX/VMS computing environment, which is intended for the design and verification of large signal processors implemented with Gallium Arsenide semicustom integrated circuits. MagiCAD is not a commercial product, but is funded by Darpa. It was developed at the Special Purpose Processor Development Group at Mayo Foundation in Rochester, Minnesota. It has been installed in two university sites under Darpa sponsorship. Contact me for further information. Kevin Buchs (buchs@mayo.com) Mayo Foundation (507)284-0009 Rochester, MN