vhdl@ee.pitt.edu (vhdl tools pseudo-user) (01/11/91)
Archive-name: languages/vhdl/pitt-vhdl/1991-01-10
Archive-directory: ee.pitt.edu:/pub/vhdl-info/ [130.49.15.1]
Original-posting-by: vhdl@ee.pitt.edu (vhdl tools pseudo-user)
Original-subject: Re: Pittsburgh Simulator (fwd from comp.lsi)
Reposted-by: emv@ox.com (Edward Vielmetti)
Thought I'd post the latest information on our VHDL tools.
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* This is the file README available by anonymous ftp from *
* ee.pitt.edu (130.49.15.1) in pub/vhdl-info *
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This directory pub/vhdl-info contains the following files:
File Description
---- -----------
README this file
letter.txt instructions on how to order the VHDL software
barrel.vhdl a trivial example of a barrel shifter
pulse.vhdl a 3-gate pulser
mult.vhdl three examples of a shift and add multiplier
All of the files listed below are in Postscript form.
license.PS license agreement for the software
assurance.PS export assurance letter for the software
vcomp.PS man page for the VHDL compiler
vsim.PS man page for the VHDL simulator
waveform.PS man page describing how to generate ascii waveforms
ivf.PS man page describing the
tech_report.PS a paper which details some implementation details
of the vhdl compiler and simulator
main_vhdl_over.PS set of slides providing an overview of VHDL
main_vhdl_syntax.PS set of slides illustrating VHDL supported
vhdl.1-23.PS set of slides on basic vhdl usage with examples
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Dear Sir or Madam:
I am writing to let you know that we are ready to release the new
version of our VHDL tools. The two main tools are vcomp, a VHDL 1076B
parser-compiler, and vsim an interactive simulator. Vcomp parses the
complete language but only generates output for a small, but useful,
subset of the language. Process statements are compiled into C source
code for run time linking with the simulator vsim. We are including
source code in this distribution, including all the parsing tables
etc. We have used bison, the GNU version of yacc for our parser. We
also are distributing a small set of examples and some "courseware"
which we use when we lecture to our students about VHDL in our digital
design and VLSI courses.
The software is all "Copyright University of Pittsburgh" and we are
issuing a non-exclusive, non-transferable license, the software is not
"public domain". Our purpose is to let more people have access to the
VHDL language for experimentation and research, not to support
commercial products.
We are distributing the software on Sun cartridge tapes for a fee of
$150. Tapes will be written in "Unix tar" format. Unfortunately, we
do not have the staff to answer phone questions. We will try to
respond to computer and U.S. mail requests. If you want a copy of the
tools, please read and sign the accompanying license agreement and
letter of assurance, and send a check made out to "Department of
Electrical Engineering, University of Pittsburgh" for $150 to:
Prof. Steven Levitan
Department of Electrical Engineering
348 Benedum Engineering Hall
University of Pittsburgh, 15261
Internet: vhdl@ee.pitt.edu
Just to let you know, we are currently working with our colleagues at
Penn State University to broaden the set of tools we will distribute
to include the rest of the Keystone synthesis tools, these allow our
students to go from VHDL into CMOS VLSI layouts, I will let you know
when that extended package is available and how to get that in the
near future.