mmm@cup.portal.com (Mark Robert Thorson) (06/14/90)
I'm not familiar with the architectural requirements for Mach, but I can tell you a little about the 88000 and 860 with regard to multiprocessor cache coherence with shared main memory. The 88200 implements a form of Goodman's write-once protocol. In this protocol, the first write to a cache line is treated as a write-through, so that it's visible on the system bus. This updates memory and invalidates the line in other snooping 88200's on the system bus. After the initial write-through, the line can be presumed to be exclusive, so subsequent writes can be treated as though the line were in copyback mode. The 860 implements no form of multiprocessor cache coherency. Even adding an external cache is a problem, because the 860 (unlike the 486) does not allow an invalidation cycle to be driven into the cache. Nor does it allow a cache flush from hardware. I suppose the intent of the designers was that software would map shared memory areas as non-cachable. Note that the 860 has virtual tags, hence it would be difficult to provide a snooping capability on the 860.