grenley@nsc.nsc.com (George Grenley) (11/02/88)
A person who shall remain nameless, while commenting on the lack of parity on NeXTs, mentioned that the 80X86 family had a "design flaw" in that one could not disable NMI without external hardware. I am no fan of Intel or its machines, but this is a flat-out dumb remark. NMI is not SUPPOSED to be maskable. That's why they call it non-maskable. I know of no uP which has a maskable NMI. Intel did it right. It's IBM, with their incredibly kludgy, screwed up, committe'd to death AT design that is in error. Buy a Mac!
james@bigtex.cactus.org (James Van Artsdalen) (11/03/88)
Since this isn't really a NeXT issue, I've forwarded to c.s.i.p. In <7465@nsc.nsc.com>, grenley@nsc.nsc.com.UUCP (George Grenley) wrote: > A person who shall remain nameless, Many years ago my parents gave me a name I am now quite fond of, and I think I'll keep it. > while commenting on the lack of parity on NeXTs, mentioned that the > 80X86 family had a "design flaw" in that one could not disable NMI > without external hardware. That's not quite what I said. For reference: For those not aware: the Intel 80x88 family has a design flaw that requires external hardware to disable NMI. Without such hardware it is not possible to prevent the system from randomly crashing when NMIs are used. What I meant was that it was necessary to have such hardware, not that Intel should have built it in. Indeed, Intel should have prevented the problem by better design in the first place. > I am no fan of Intel or its machines, but this is a flat-out dumb remark. > NMI is not SUPPOSED to be maskable. That's why they call it non-maskable. > I know of no uP which has a maskable NMI. Well... It is necessary to mask even NMI in any situation where the interrupt table or stack is unstable. On the 386 this can happen because (1) the stack pointer has two halves, SS and SP, and (2) there is no atomic way to switch modes and change interrupt tables. In case (1), the original 8088 just died, and I don't believe there was any way to prevent it. In the 386 and 286 (and later 8088s I think), the "MOV SS,reg/mem" instruction implicitly "disables" NMI checking after the instruction, so that the sequence mov ss,stack_ss mov sp,stack_sp was atomic with regards to interrupts. Case (2) still affects the 386 as far as I know. Here the problem is a result of the fact that the interrupt table has different formats in different modes. There is always a window for an NMI between when the table pointer is changed and when the mode is switched. The 030 obvious suffers from none of this: the stack pointer is all in one piece, and there aren't any "modes" to switch between. > Intel did it right. It's IBM, with their incredibly kludgy, screwed up, > committe'd to death AT design that is in error. Not true. Intel got it wrong. IBM did the only thing that could make the machine work. > Buy a Mac! Buy a NeXT! -- James R. Van Artsdalen james@bigtex.cactus.org "Live Free or Die" Home: 512-346-2444 Work: 338-8789 9505 Arboretum Blvd Austin TX 78759