jvkelley@watcgl.waterloo.edu (Jeff Kelley) (06/05/90)
I'm interested in the multiprocessing support provided by the NeXT bus interface chip. Does it have a location monitor (i.e. source processor writes to a location on target processor and raises an interrupt on the target processor), a hardware FIFO (similar to location monitor but data is captured from the bus during the write cycle and stored in a FIFO queue for later extraction by the target processor, typically information like the number of the source processor is sent), or other support for multiple processors? (If it has a FIFO, how deep and how wide?) -- Jeff Kelley National Research Council of Canada, Ottawa uunet!watmath!watcgl!jvkelley tel: (613) 990-5924