ramsdell@linus.mitre.org (John D. Ramsdell) (07/09/90)
It seems that NeXT is committed to the use of antiquated CPU's. The best reason I have heard is that the company cannot afford to support two platforms which are not binary compatible. This excuse was stated by Bruce Henderson in issue 7 of NeXT User's Journal. While there may be sound reasons why NeXT cannot provide a RISC CPU, I see no reason why another vendor could not sell an add-on board which could plug into one of the extra slots. This would require the release of the missing bus chip, but I image the new board could be priced to be competitive with the `40 upgrade. I would be happy to run my CPU intensive computations on say a MC88000 which communicates to the rest of the system via Mach messages. Are there any RISC-based coprocessors on the horizon? John
mek4_ltd@uhura.cc.rochester.edu (Mark Kern) (07/10/90)
In article <112780@linus.mitre.org> ramsdell@mitre.org writes: >It seems that NeXT is committed to the use of antiquated CPU's. Are CISC's antiquated? I am not an engineer, but I have heard conflicting stories in the RISC vrs. CISC debate. A few posts back, someone said (I'm afraid I forgot who) that the NeXT people furiously defended CISC processors over RISC. Are they blind, or are we (the user public) being blinded by hoopla and hype concerning RISCs? For example, people have told me that you cannot compare a RISC to CISC by comparing MIPS, because of the difference in the two architectures. Thus, some people I know are prone to saying CISC will give you such and such Real Mips, while RISC will give you RISC Mips. The end result is that a RISC chip may have blindingly great MIP stats, but actually be no faster than a CISC chip rated at half that. With the emergence of the 68040, I've heard that they have preserved an extensive CISC instruction set, while getting many instructions to execute in one cycle like a RISC. Current RISC chips may blow the doors off current CISC chips, but are we reaching a hybrid as in the 68040? Is the 68040 a come-back for the CISCs? Or has RISC been a lot of hype and exageration? Mark Kern -- ========================================================================= Mark Edward Kern, mek4_ltd@uhura.cc.rochester.edu A.Online: Markus Quagmire Studios U.S.A. "We not only hear you, we feel you !" =========================================================================
jacob@gore.com (Jacob Gore) (07/10/90)
/ comp.sys.next / mek4_ltd@uhura.cc.rochester.edu (Mark Kern) / Jul 9, 1990 / > For example, people have told me that you cannot compare a RISC > to CISC by comparing MIPS, because of the difference in the two > architectures. Thus, some people I know are prone to saying CISC will > give you such and such Real Mips, while RISC will give you RISC Mips. The > end result is that a RISC chip may have blindingly great MIP stats, but > actually be no faster than a CISC chip rated at half that. "1 MIPS" now generally means "the speed of a VAX-11/780". They run various benchmarks on the CPU to be rated, then divide the resulting speed by the speed of that same benchmark on a 780. This is less meaningless than just comparing instructions/second of each chip (unless the chips have the same instruction set). Of course, one still needs to see if how well the benchmarks correspond to the use one will put the machine to, and the CPU speed is just one of the factors that determine the speed of the machine. Jacob -- Jacob Gore Jacob@Gore.Com boulder!gore!jacob
khb@chiba.Eng.Sun.COM (Keith Bierman - SPD Advanced Languages) (07/10/90)
...risc vs. cisc...
Please don't rehash this.
Read the Hennessy/Patterson book "Computer Arch. A Quantiative
Approach"
--
Keith H. Bierman |*My thoughts are my own. !! kbierman@Eng.Sun.COM
It's Not My Fault | MTS --Only my work belongs to Sun* khb@chiba.Eng.Sun.COM
I Voted for Bill & | Advanced Languages/Floating Point Group (415 336 2648)
Opus<khb@eng.sun.com> "When the going gets Weird .. the Weird turn PRO"bruce@atncpc.UUCP (Bruce Henderson) (07/13/90)
In article <112780@linus.mitre.org>, ramsdell@linus.mitre.org (John D. Ramsdell) writes: > of the system via Mach messages. Are there any RISC-based > coprocessors on the horizon? > > John 8-) Yea, They call it an RS/6000! 8-) Bruce