matthews@umd5.umd.edu (Mike Matthews) (11/13/90)
I would have done a Followup to this, but is-next does not have permission to post news, and I don't rn on umd5 here because it's usually loaded down way too much... Anyway, after reading all of this discussion about speeds of the SPARC 2 and all, and I have a question. The SPARC 2 is a RISC machine, right? So it's 28 MIPS is fast, but each instruction isn't doing all that much. But the NeXT's 15 MIPS is CISC architecture, so each instruction does a full command, so to speak. Assuming a CISC instruction is approximately equal to three or so (on average) RISC instructions... ? Am I missing something? -- "The shortest distance between two points is under construction." - UMCP motto Mike Matthews (matthews@umd5.umd.edu, bitnet matthews@umdd)
castor@embezzle.stanford.edu (Castor Fu) (11/14/90)
This may seem like a silly point, but all this talk about nitty gritty architectural questions gets rehashed to no end in comp.arch, and the upshot seems to always be: Run the programs YOU will be running on the machines you are interested in, and measure the speed. Any other measure (MIPS, MHz etc.) is likely to mislead you. Any single number is likely to mislead you as well, as different computers can perform better or worse on different programs. Overall performance depends on so many factors nowadays Various companies (MIPS, Sun, DEC?, IBM etc.) have formed a consortium, SPEC, to try to come up with a set of "representative" programs to make a more comprehensive set of benchmarks. The current test suite includes compilers, Monte Carlo simulations, typesetters, and so forth, i.e. CPU intensive tasks, some of which are floating point intensive as well. Performance is generally expressed in terms of multiples of the speed of a VAX 11/780. Computers like the SparcStation 1, or DECStation 3100 generally score around 10 times an 11/780. The higher end machines, (IBM RS6000, DECstation 5000, Sparcstation 2) will presumably be around 18 times an 11/780, with the IBM machine doing much better on the floating point benchmarks. So what I want to know is, have the SPEC benchmarks been run on the new NeXT machines? How do they perform? -Castor Fu castor@fizzle.stanford.edu
gessel@carthage.cs.swarthmore.edu (Daniel Mark Gessel) (11/14/90)
In article <7567@umd5.umd.edu> matthews@umd5.umd.edu (Mike Matthews) writes:
I would have done a Followup to this, but is-next does not have permission to
post news, and I don't rn on umd5 here because it's usually loaded down way
too much...
Anyway, after reading all of this discussion about speeds of the SPARC 2 and
all, and I have a question.
The SPARC 2 is a RISC machine, right? So it's 28 MIPS is fast, but each
instruction isn't doing all that much.
But the NeXT's 15 MIPS is CISC architecture, so each instruction does a full
command, so to speak. Assuming a CISC instruction is approximately equal to
three or so (on average) RISC instructions... ?
Am I missing something?
I don't think so. There was a talk at swat here recently by the project leader
(who's name I forget) of the 68040 processor. I've also read a little about
the architecture (the guys talk was for engineering majors and was mostly
about the process of designing a larger than 1M transistor chip).
I haven't compared the two types of processors, and I'm just learning 68000
assembly for a compilers project, but my impression is that the above is
correct. The integer pipeline is 6 stages, and my suspicion is that those
stages can do quite a bit, although I don't know the equivalence to a RISC
command. They did alot of tracings on 68000 systems, and the '040 has optimized
instructions for the most common commands. The most often used instructions
are executed one per cycle.
Before I go on to create any wild rumors about CISC vs. RISC,
anybody know where I could get
user's manuals etc for the sparc chips? I'm no hardware expert, but I think
I know enough (and if I don't, I know someone who does) to make a decent
comparison. I could even go as far as trying to figure out certain kinds
of functions and try to optimize the code on both processors, if people
are really interested (and I find the time).
Or maybe somebody has already done this sort of thing in the great RISC vs.
CISC battle?
Dan
--
Daniel Mark Gessel Independent Consultant
Internet: gessel@cs.swarthmore.edu
My opinions are mine. (a -> a)romero@arisia.Xerox.COM (Antonio Romero) (11/15/90)
In article <7567@umd5.umd.edu> matthews@is-next.umd.edu (Mike Matthews) writes: >The SPARC 2 is a RISC machine, right? So it's 28 MIPS is fast, but each >instruction isn't doing all that much. >But the NeXT's 15 MIPS is CISC architecture, so each instruction does a full >command, so to speak. Assuming a CISC instruction is approximately equal to >three or so (on average) RISC instructions... ? >Am I missing something? Yes, you are. These days benchmarks are usually "normalized" so that the amount of real work accomplished by a 1 MIP machine is equivalent to the amount of "real work" accomplished by a VAX 11/780. While benchmark ratings can of course be rigged by recoding the tests, there is *some* consistency because of this kind of normalization. So, the claim is that a NeXT is 15x the speed of a 780, and the Sparcstation 2 (Sparcstation ][? ;) ) is about 28x. -Antonio Romero romero@arisia.xerox.com
bostrov@storm.UUCP (Vareck Bostrom) (11/15/90)
In article <7567@umd5.umd.edu> matthews@is-next.umd.edu (Mike Matthews) writes: >The SPARC 2 is a RISC machine, right? So it's 28 MIPS is fast, but each >instruction isn't doing all that much. Yeah, they are talking about dhrystone MIPS where 1 MIPS = ~1200 or ~1700 dhrys. I don't have the exact number. Read any IBM RS/6000 ad where they have the SPARC 1 15 MIPS, DEC 3100 so and so mips RS/6000 1 billion MIPS blah blah, you will find in the fine print "1 MIPS equals 1727 dhrystones per second" or something. On a VAX 11/780 I believe that it takes about one million instructions to do 1727 dhrys.... There you are.
gilgalad@caen.engin.umich.edu (Ralph Seguin) (11/15/90)
>In article <7567@umd5.umd.edu> matthews@is-next.umd.edu (Mike Matthews) writes: >>The SPARC 2 is a RISC machine, right? So it's 28 MIPS is fast, but each >>instruction isn't doing all that much. The POWER (Performance Optimized With Enhanced RISC) chips used in the RS/6000s have several execution units. Quite a bit can be done by each instruction. They use a different senses of the word RISC. What they mean is reduce the number of cycles per instruction. On the 320, they were averaging LESS than 1 cycle per instruction. This is nonsense. The RS/6000s SCREAM. I have been using them for quite some time now. They give SPECmarks which kill every other machine at that price level. There is, of course, the matter of software. AIX is still buggy. See ya, Ralph Ralph Seguin gilgalad@dip.eecs.umich.edu 536 South Forest Apt. #915 gilgalad@caen.engin.umich.edu Ann Arbor, MI 48104 (313) 662-4805
lange@lanai.cs.ucla.edu (Trent Lange) (11/15/90)
In article <643@storm.UUCP> bostrov@storm.UUCP (Vareck Bostrom) writes: > >Yeah, they are talking about dhrystone MIPS where 1 MIPS = ~1200 or ~1700 >dhrys. I don't have the exact number. Read any IBM RS/6000 ad where they >have the SPARC 1 15 MIPS, DEC 3100 so and so mips RS/6000 1 billion MIPS >blah blah[...] Wow! A billion MIPS! Get those things running any faster and even X might run with decent response times. :-) - Trent Lange -- ************************************************************************ * UCLA: Perfecting the art of arthroscopic surgery. * ************************************************************************
jacob@gore.com (Jacob Gore) (11/16/90)
/ comp.sys.next / lange@lanai.cs.ucla.edu (Trent Lange) / Nov 15, 1990 / > Wow! A billion MIPS! Get those things running any faster and even X > might run with decent response times. :-) Hah. That's nothing. One salesman measured the speed of his product (forgot what compnany it was) in MIPS per second. Give me an accelerating machine any day! Jacob -- Jacob Gore Jacob@Gore.Com boulder!gore!jacob