gt5223b@prism.gatech.EDU (Doug Berkland) (03/09/91)
What are non-parity SIMS?
Thanks in advance.
--
Doug Berkland Internet: gt5223b@hydra.gatech.edu Phone: (404)676-9068
uucp: ...!{decvax,hplabs,ncar,purdue,rutgers}!gatech!prism!gt5223b
Georgia Institute of Technology, Atlanta GA 30332 <<Electrical Engineer>>
"If I don't have it, how do I know I don't want it?" --mebennett@mp.cs.niu.edu (Scott Bennett) (03/11/91)
In article <23938@hydra.gatech.EDU> gt5223b@prism.gatech.EDU (Doug Berkland) writes: >What are non-parity SIMS? Non-parity SIMMs have only eight chips, i.e. eight bits per byte. Parity SIMMs have a ninth chip (nine bits per byte) that allows the surrounding hardware to detect, and in many systems correct, single-bit errors. Some systems are also able to detect, but not correct, double- bit errors. Another answer to your question is that it depends on what you're using the memory for. If you're using it for any purpose where relia- bility is important (e.g. numerical applications, an operating system whose integrity you care about, etc.), then the answer is that non- parity SIMMs are worthless. That's why computer manufacturers abandoned non-parity memory by the 1950's. On the other hand, if reliability is not important to you, then non-parity SIMMs represent perhaps a $4-$10/SIMM savings on a one-time basis for 1Mbx8 SIMMs (as opposed to 1Mbx9, i.e. w/parity bits) or perhaps $15-$35/SIMM for 4Mbx8's vs. 4Mbx9's. The new, 68040-based NeXTs can be configured either w/parity or w/o parity, as you prefer. I am told, however, that NeXT has screwed up the hardware design in those machines in a way that causes the use of parity memory to introduce wait states. The old, 68030-based NeXTs cannot use parity memory. >Thanks in advance. >-- >Doug Berkland Internet: gt5223b@hydra.gatech.edu Phone: (404)676-9068 >uucp: ...!{decvax,hplabs,ncar,purdue,rutgers}!gatech!prism!gt5223b >Georgia Institute of Technology, Atlanta GA 30332 <<Electrical Engineer>> > "If I don't have it, how do I know I don't want it?" --me Scott Bennett, Comm. ASMELG, CFIAG Systems Programming Northern Illinois University DeKalb, Illinois 60115 ********************************************************************** * Internet: bennett@cs.niu.edu * * BITNET: A01SJB1@NIU * *--------------------------------------------------------------------* * "The good news is that Saddam Hussein will be tried for war * * crimes. The bad news is that the case will be heard by the * * Senate Ethics Committee."--quoted in _The_Wall_Street_Journal_ * **********************************************************************
waltrip@capd.jhuapl.edu (03/11/91)
In article <1991Mar11.045612.1764@mp.cs.niu.edu>, bennett@mp.cs.niu.edu (Scott Bennett) writes: > In article <23938@hydra.gatech.EDU> gt5223b@prism.gatech.EDU (Doug Berkland) writes: >>What are non-parity SIMS? [...] > The new, 68040-based NeXTs can be configured either w/parity or > w/o parity, as you prefer. I am told, however, that NeXT has screwed > up the hardware design in those machines in a way that causes the use > of parity memory to introduce wait states. Hmmm. I'm not sure this is a screw-up. I believe the wait states are only introduced when accessing memory--but most of the time (if all goes according to plan :^) you'll be running out of cache. In practice, I doubt that the introduction of wait states will have much impact. [...] c.f.waltrip Internet: <waltrip@capsrv.jhuapl.edu> Opinions expressed are my own.
madler@pooh.caltech.edu (Mark Adler) (03/12/91)
Just to add to the misinformation about parity, I heard that the wait state for parity is added only to write cycles, not read cycles. This would make sense (since the parity check on reads can go on in parallel with using the read data), and would further reduce the impact of the wait states, even after taking into account cache hits. Maybe Conrad can fill us in on the performance impact of parity. Mark Adler madler@pooh.caltech.edu
bennett@mp.cs.niu.edu (Scott Bennett) (03/12/91)
In article <1991Mar11.101750.1@capd.jhuapl.edu> waltrip@capd.jhuapl.edu writes: >In article <1991Mar11.045612.1764@mp.cs.niu.edu>, bennett@mp.cs.niu.edu (Scott > Bennett) writes: >> In article <23938@hydra.gatech.EDU> gt5223b@prism.gatech.EDU (Doug Berkland) > writes: >>>What are non-parity SIMS? > [...] >> The new, 68040-based NeXTs can be configured either w/parity or >> w/o parity, as you prefer. I am told, however, that NeXT has screwed >> up the hardware design in those machines in a way that causes the use >> of parity memory to introduce wait states. > Hmmm. I'm not sure this is a screw-up. I believe the wait states are > only introduced when accessing memory--but most of the time (if all If it introduces wait states, then it is indeed a design flaw. Even IBM pee cees and clones thereof have parity memory that does not introduce wait states by virtue of being parity memory. If junky hardware like those machines can do it, any manufacturer's (yes, even NeXT's) ought to do it. > goes according to plan :^) you'll be running out of cache. In > practice, I doubt that the introduction of wait states will have much > impact. If the data cache is write-through, not write back, it could well make quite a difference. Does anyone have a 68040 manual yet? > [...] > On another note, the memory used in both the 68030 NeXTs and the 68040 NeXTs is too slow to avoid wait states on a 25-MHz bus. Does interleaving manage to reduce the wait states actually induced to a near-zero level in the NeXTs? > >c.f.waltrip > >Internet: <waltrip@capsrv.jhuapl.edu> > >Opinions expressed are my own. Scott Bennett, Comm. ASMELG, CFIAG Systems Programming Northern Illinois University DeKalb, Illinois 60115 ********************************************************************** * Internet: bennett@cs.niu.edu * * BITNET: A01SJB1@NIU * *--------------------------------------------------------------------* * "The good news is that Saddam Hussein will be tried for war * * crimes. The bad news is that the case will be heard by the * * Senate Ethics Committee."--quoted in _The_Wall_Street_Journal_ * **********************************************************************