isbell@ucscf.UCSC.EDU (Art Isbell) (03/19/91)
In article <b2hwh6.m1u@wang.com> ice@wang.com (Fredrik Nyman) writes: >beaucham@uxh.cso.uiuc.edu (James Beauchamp) writes: > >>I am also wondering about the benchmarks in Table 2. I heard that floating >>point performance of the 040 was going to soar compared to the 030. The >>float benchmark they give only shows a 46% improvement, a long way from the >>x10 improvement I heard about last year. In the text of the article they >>make no comment about this insipid result. >All instructions on the 68882 FPU didn't fit in the 68040. Those that >didn't make it on chip are emulated in software and are a *LOT* slower >than the on-chip fp instructions. When I asked a NeXT compiler guy about this at a BaNG meeting, he said that NeXT wanted to maintain binary compatibility between '030 and '040 models. In order to do this, NeXT had a couple of choices: optimize '040 floating-point performance by writing the compiler to call software routines for all floating-point operations not implemented in silicon in the '040 and thus force '030 models to use these slower software routines rather than the much faster 68882 instructions; maintain '030 performance by calling 68882 floating-point instructions that require slow trapping on the '040. NeXT chose the latter rather than the former. The performance hit for the '040 is about a factor of 3 for those trapped instructions versus a performance hit of about a factor of 10 for the '030 had option 1 been selected. He indicated that in the future (once few '030's still remain), NeXT will rewrite the compiler to take full advantage of the '040. So everyone upgrade soon so we can get "full performance" from the '040. '030 performance by not allowing '030 models to take advantage of the -- _____ ____ Art Isbell |\ | | | | \ 315 Moon Meadow Lane NeXT Registered Developer | \ | ___ |____| | | Felton, CA isbell@ucscf.UCSC.EDU | \ | |___| | \ | | 95018-9442 (408)438-4736(B) | \| |___ | \ |___/ (408)335-1154(H)