cmaeda@a.gp.cs.cmu.edu (Christopher Maeda) (04/25/91)
I went to a talk on the 68040 last week. Neat chip. Performance-wise, there isn't much difference between the supposedly-CISC 68040 and a RISC chip. The 040 has a pipeline depth of 6 or 7 clocks (I can't remember the slide exactly) while the MIPS chip has a depth of 5, at least according to Hennesey&Patterson's book which was based on the R2000 and R3000. Both chips get 1 clock per instruction on straight line code. The 040 takes 2 clocks for taken branches. I forget what the MIPS chip takes. So the only differences I can see between an 040 and an R3000 are the pipeline depth, the amount of cache, and the number of registers. The R3000 is superior in all three of these categories (it has oodles of registers and uses off-the-shelf SRAM's for cache) which explains the slightly better performance. They both have similar (ie memory<->register) instruction sets so the CISC mips vs RISC mips is a non-argument. On the other hand, a PC based on the R3000 is likely to be out of most people's reach for at least another year. It took Moto 3 years to design and build the thing. The guy giving the talk said it's taken them about 3 years for each chip in the 68k family. (68050 in 1993?) Their cad tools have been keeping pace with the increased complexity. They used a fast prototype approach to debug the chip since they didn't have enough time to do simulations of the full chip (1.2 million transistors). To make up for it, they used a scanning electron microscope to find bugs and (get this) a focused ion beam to fix them. They also put sets of spare gates in various places on the chip so they could splice them in with the ion beam when they needed to. Who says you can't have jumper wires in silicon? -- Chris Maeda, Grad Student from Hell |Mail: cmaeda@cs.cmu.edu care bear |UUCP: get a real mailer alone in the microwave |$$^X. so hard to clean the appliance |$$u
melling@cs.psu.edu (Michael D Mellinger) (04/25/91)
In article <12787@pt.cs.cmu.edu> cmaeda@a.gp.cs.cmu.edu (Christopher Maeda) writes:
So the only differences I can see between an 040 and an R3000
are the pipeline depth, the amount of cache, and the number
of registers. The R3000 is superior in all three of these
categories (it has oodles of registers and uses off-the-shelf
SRAM's for cache) which explains the slightly better performance.
They both have similar (ie memory<->register) instruction sets
so the CISC mips vs RISC mips is a non-argument. On the other hand,
a PC based on the R3000 is likely to be out of most people's
reach for at least another year.
I think an R3000 performs more than slightly better than the 68040.
The 68040 seems to only SPEC at around 12. The R3000 is more like a
SPEC of 18 or 19(I think).
It took Moto 3 years to design and build the thing. The guy giving
the talk said it's taken them about 3 years for each chip in the
68k family. (68050 in 1993?) Their cad tools have been keeping pace
with the increased complexity. They used a fast prototype approach to
debug the chip since they didn't have enough time to do simulations of
the full chip (1.2 million transistors). To make up for it, they used
a scanning electron microscope to find bugs and (get this) a focused
ion beam to fix them. They also put sets of spare gates in various
places on the chip so they could splice them in with the ion beam
when they needed to. Who says you can't have jumper wires in
silicon?
The 68040 was announce around 2 years ago. Didn't both Intel and
Motorola announce their chips in the summer of 89? Except of course,
Intel has been shipping for 2 years. I have an issue of Byte magazine
from 1989 where they talk about the first 486 machines.
Did Motorola give any performance claims about the 050? I think that
it's pretty safe to assume that next years R4000 is going to smoke the
050 which will be lucky if it's out the door by 1994.
-Mike