dejnsen@caen.engin.umich.edu (Nik Anthony Gervae) (04/28/91)
My architecture professor, Y N Patt, looks at the whole thing on a graph: | E| F| F| I| C| I| E| ---> <--- N| . . C| . . Y| +------------------------------------- COMPLEXITY RISC (Berkeley) CISC (Vax) That is, early RISC chips were just as inefficient (although in different ways) as CISC chips (CISC better at floating point math, RISC at integer and stuff), but both are moving toward a more efficient middle ground, using advantages learned from both schools -- sometimes you *want* a post-increment memory access in one instruction (like the RS6000 I'm writing this on--marketed as "RISC"), sometimes you *want* more simple instructions that execute in one cycle. My professor said exactly what Scott Hess said earlier: RISC is good marketing these days, and little else. You say it's RISC, people laud and buy it. The trend is more toward "HISC" (to coin an acronym): Hybrid Instruction Set Computer...... My NeXT is plenty fast with a 68040 (could use more than 8Meg RAM tho). If and when NeXT or Motorola incorporate *those features of RISC* that result in performance gains, I'll be even happier. But if they completely buy the hype, I'll wonder just how smart they are (I'll still use their products). Just my tuppence. Nik -- / Nik Gervae aka dejnsen@caen.engin.umich.edu | "It'll be finished next week, \ | CS/Linguistics stud. & NeRD at UM (go blow) | I promise!"--me | | | | | **When all else fails, bug someone who | "Just say an iguana chewed | \ knows (not me!). | up your textbook."--Jason Fox /