andrey@beyond.cs.caltech.edu (Andre Yew) (05/05/91)
Sorry about the very long delay of this summary, if anyone's still interested. But a while ago, I asked about interfacing the DSP56001 to DRAM and promised I would post a summary. Well here it is. Personally, I will probably be trying the Motorola method. Thanks to everyone who sent me advice. ------------------------------ From: p554mve@mpirbn.mpifr-bonn.mpg.de (Michael van Elst) In article <andrey.670552848@beyond> you write: > I'm starting to design a project around the Motorola DSP56001 and need >more memory than the 64K of SRAM that the 56001 can see. So, has anyone out >there hooked up DRAM, by any means, to the 56001? I'm using 256kx4bit DRAMs with the 56001. These are DRAMs that know about fast pagemode cycles. 6 RAMs give a 24bit word. I pass the low 10 address bits directly to the RAMs and use a PAL to decode two 1K areas in the address space. In Space 1, a write to 'X' memory starts a RAS cycle, a write to 'Y' memory stops the RAS cycle. In Space 2, a read or write is used to strobe CAS. I'm using the /BS signal directly as CAS. Since the /WR signal is too early for the RAMs it has to be delayed about 30-40 ns. The processor does all refresh cycles that are interleaved with regular accesses in the program. As you can see it is much more efficient to read DRAM pages sequentially since each RAS consumes two extra cycles (plus the CAS cycle). The logic described above makes it possible to use a single write to L:-space to generate a refresh cycle. The RAMs are Hitachi 514256-10S which are fast enough for a 20MHz main clock. When using a 27MHz clock you can't use writes to L: space since that violates the minimum RAS precharge time of the DRAMs but they are fast enough for no-waitstate pagemode cycles. Hope this helps, -- Michael van Elst UUCP: universe!local-cluster!milky-way!sol!earth!uunet!unido!mpirbn!p554mve Internet: p554mve@mpirbn.mpifr-bonn.mpg.de "A potential Snark may lurk in every tree." ------------------------------ From: roman@jethro.sps.mot.com (Roman Robles) Andre, we have an applications note which describes a DRAM Interface to the DSP56001. Please call me or send me your mailing address and I will be happy to send you a copy. Regards Roman Robles MOTOROLA DSP Operations Austin, Tx 512-891-3715 From: roman@jethro.sps.mot.com (Roman Robles) The DSP Applications HOTLINE number is 512-891-3230 and it is manned 09:00 to 17:00 CST on normal workdays. Please leave a phone no. and a brief message if the line is busy. ------------------------------ From: Chuck Pateros <pateros@ecse.rpi.edu> I just build a ram board for our ADSP board (the one from moto) I wanted to use DRAM, but in the end, I used SRAM. I used 16 32K x 8 chips to give me 256K x 16 (audio storage). The circuit is really simple - 16 SRAMS and a 74F138. I use port lines to give me the extra address lines. You didn't say in your article how much extra memory you need, but if you want a simple design, consider SRAMS. Chuck p.s. 128K x 8 chips are coming down in price (I got the 32K x 8 chips for free) ------------------------------ From: rogerc@qiclab.scn.rain.com (Roger Conley) The 56001 is inherently designed to do this. The address and data lines are tri-stated on the 56001 so that memory can be double buffered. Using this scheme a bank of memory can be either in the 56001 memory space or the host computer's memory space. Other combinations of this technique are endlless More than on bank can be double buffered. You can have two banks flip-flop where one is in the 56001 and the other is in the cpu and then they switch vica-versa and on and on. These are just simple examples. -- Roger Conley rogerc@qiclab.scn.rain.com ------------------------------ -- Andre Yew andrey@through.cs.caltech.edu (131.215.131.169)