cyliao@eng.umd.edu (Chun-Yao Liao) (05/25/91)
well, it seems there are interest of putting more 68040 to the work...
I just read an article, I'll try to pick up some points
o Normally a RISC processor would use almost 100% of the local memory
bus bandwidth and a CISC processor would use almost 80%.
so dual RISC seems to be impossible, and, for CISC,
if using same processor in a dual CPU design, both processors share
access to memory, that means, each processor needs 80% of memory bandwidth,
a total of 160% is needed. Therefore, increase of performance is very
limited
o internal cache significantly reduces the need of accesing local memory bus
o burst fill mode is efficient to fill up cache memory
68040 is the first Moto CISC to make a dual-CPU practical, it has internal
cache AND burst-fill mode
o CPU Bus occupancy
68010 90%
68020 70%
68030 50%
68040 40%
although, 68030 almost could be used for dual-cpu processing, it lacks
circutry needed to handle multiple processors
o each 68040 takes 40% bus bandwidth, 2 of them makes 80%, way to go!
performance almost doubles!
o the speed of data transfer betwen processors also matters... if both
processors are located on different boards, then the transfer rate
of the bus betwen boards will be the bottle neck
So I'd say, perhaps putting 2 68040 on a same mother board can probably
give more than 30 MIPS at 25 MHZ, and when clock rate being pushed to
say 50 MHZ, a 60+ MIPS may be possible! :-) am I dreaming or what?
--
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