cyliao@eng.umd.edu (Chun-Yao Liao) (05/26/91)
I don't think my last attept posting this article was successful, so here
goes again.
well, it seems there are interest of putting more 68040 to the work...
I just read an article, I'll try to pick up some points
o Normally a RISC processor would use almost 100% of the local memory
bus bandwidth and a CISC processor would use almost 80%.
so dual RISC seems to be impossible, and, for CISC,
if using same processor in a dual CPU design, both processors share
access to memory, that means, each processor needs 80% of memory bandwidth,
a total of 160% is needed. Therefore, increase of performance is very
limited
o internal cache significantly reduces the need of accesing local memory bus
o burst fill mode is efficient to fill up cache memory
68040 is the first Moto CISC to make a dual-CPU practical, it has internal
cache AND burst-fill mode
o CPU Bus occupancy
68010 90%
68020 70%
68030 50%
68040 40%
although, 68030 almost could be used for dual-cpu processing, it lacks
circutry needed to handle multiple processors
o each 68040 takes 40% bus bandwidth, 2 of them makes 80%, way to go!
performance almost doubles!
o the speed of data transfer betwen processors also matters... if both
processors are located on different boards, then the transfer rate
of the bus betwen boards will be the bottle neck
So I'd say, perhaps putting 2 68040 on a same mother board can probably
give more than 30 MIPS at 25 MHZ, and when clock rate being pushed to
say 50 MHZ, a 60+ MIPS may be possible! :-) am I dreaming or what?
--
cyliao@bagend.eng.umd.edu o Q. Who am I?
NeXTmail o.k. o A. A NeXTed person with 320meg HD and OD
I have MailService o An Apple // guy
and a 2400 modem w/o MNP o An airplane pilot (I hope)kls30@duts.ccc.amdahl.com (Kent L Shephard) (05/31/91)
In article <1991May25.213046.20342@eng.umd.edu> cyliao@eng.umd.edu (Chun-Yao Liao) writes: >I don't think my last attept posting this article was successful, so here >goes again. > >well, it seems there are interest of putting more 68040 to the work... >I just read an article, I'll try to pick up some points > >o Normally a RISC processor would use almost 100% of the local memory ~~~~~~~~~~~~~~~~~~~ This isn't true. Assuming a load or a store every cycle this would happen but a load or store doesn't happen that often. > bus bandwidth and a CISC processor would use almost 80%. ~~~~~~~~~~~ Not nearly this high. Probably about half that. The question is not how busy memory is but how fast can it provide data to the cpu. > > so dual RISC seems to be impossible, and, for CISC, ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Only if you assume that neither has a cache. > if using same processor in a dual CPU design, both processors share > access to memory, that means, each processor needs 80% of memory bandwidth, > a total of 160% is needed. Therefore, increase of performance is very > limited This is why in multiprocessor and parallel processor designs each CPU has a local cache. The alternatives are multiport memory that supports simultaneous reads and abitrates writes or high order interleaving of memory banks. > >o internal cache significantly reduces the need of accesing local memory bus >o burst fill mode is efficient to fill up cache memory > >68040 is the first Moto CISC to make a dual-CPU practical, it has internal >cache AND burst-fill mode > >o CPU Bus occupancy > 68010 90% > 68020 70% > 68030 50% > 68040 40% > although, 68030 almost could be used for dual-cpu processing, it lacks > circutry needed to handle multiple processors ~~~~~~~~~~~~~~~~~~~~~~~~~ This is why you design a system where each processor has a local cache and use one of the following protocols MSI, MESI, or MOESI which give you cache coherency in multiprocessor systems. > >o each 68040 takes 40% bus bandwidth, 2 of them makes 80%, way to go! > performance almost doubles! ~~~~~~~~~~~~~~~~~~~~~~~~~~ If you are using them as a loosly coupled system - ie. networked then you get a speed increase when running multiple tasks. But that means no shared memory. This also means you need to run two copies of the OS. You probably mean a tightly coupled system, and if that is the case one cpu runs the OS and the other is the slave. If this is the case you lose roughly 15-20% of the sum to communication and task dispatch overhead. > >o the speed of data transfer betwen processors also matters... if both > processors are located on different boards, then the transfer rate > of the bus betwen boards will be the bottle neck You would not use the NeXTbus for communication between the processors. You would use a bus dedicated to cpu communication (more money) that way you get better performance. Otherwise you might as well just use some network connectors. > > So I'd say, perhaps putting 2 68040 on a same mother board can probably > give more than 30 MIPS at 25 MHZ, and when clock rate being pushed to ~~~~~~~~~~ Don't fool yourself. 2 processors in a system D.N.E. 2 X performance of one. You neglected some overhead. Real performance in a multiprocessor system with 2 '040s would be about 25-27 mips sustained. Peak numbers mean nothing. Because the cpu waits for I/O. > say 50 MHZ, a 60+ MIPS may be possible! :-) am I dreaming or what? > >-- >cyliao@bagend.eng.umd.edu o Q. Who am I? > NeXTmail o.k. o A. A NeXTed person with 320meg HD and OD > I have MailService o An Apple // guy > and a 2400 modem w/o MNP o An airplane pilot (I hope) You should pick up Hennessy and Patterson - Computer Architecture A Quantitive Approach, read some papers published by the IEEE on parallel processing systems and/or pick up a text book on parallel and multiprocessor computer systems. -- /* -The opinions expressed are my own, not my employers. */ /* For I can only express my own opinions. */ /* */ /* Kent L. Shephard : email - kls30@DUTS.ccc.amdahl.com */